English
Synopsys PrimeTime Advanced On-chip Variation Analysis Enables Renesas to Accelerate Timing Closure at 65-nm and Below
PrimeTime Technology Brings Margin Reduction Benefits to Broader Range of Customers and Process Technologies
MOUNTAIN VIEW, Calif. -- April 14, 2009 -- Synopsys, Inc. , a world leader in software and IP for semiconductor design and manufacturing, today announced that Renesas Technology Corp. has deployed Synopsys' PrimeTime® advanced on-chip variation (OCV) capability to help accelerate timing closure for 65-nanometer (nm) and below system-on-chip (SoC) designs. PrimeTime advanced OCV analysis is an efficient, easy-to-adopt solution that employs adaptive derating to accurately account for random and systematic process variations across an integrated circuit (IC). This evolutionary approach brings the margin reduction benefits of variation-aware modeling to a broader range of customers and process technologies by eliminating the need to change libraries or significantly modify design flows. PrimeTime advanced OCV has been correlated to silicon at leading semiconductor companies including Renesas, qualified and recommended by the STARC Japanese semiconductor consortium, and is part of the stage-based on-chip variation solution in the TSMC Reference Flow 9.0.
"During a recent 45-nanometer tapeout, using the PrimeTime advanced OCV feature helped us achieve a 5X reduction in the number of timing violations we needed to analyze and fix, saving us a significant amount of schedule time," said Hitoshi Sugihara, department manager of the DFM & Digital EDA Technology Development Dept., Design Technology Div., Renesas Technology. "We collaborated with Synopsys early in the development of this methodology to ensure it was easy to deploy, and have confirmed its signoff accuracy versus both HSPICE Monte-Carlo (or statistical) simulation and actual silicon. The PrimeTime advanced OCV capability is now deployed as a standard part of our timing signoff flows at 65 nanometers and below."
Synopsys' PrimeTime advanced OCV technology provides more finely-tuned design margins in timing analysis by incorporating logic-depth information to determine path-specific and cell-specific margin values. Using simple derate tables to complement the global derate methodology that has been used for many years to account for on-chip variation allows PrimeTime customers to take advantage of the more finely-tuned design margins with minimal changes to existing timing signoff scripts. The PrimeTime advanced OCV capability is part of a comprehensive set of variation-aware design solutions offered by Synopsys that also includes the PrimeTime VX statistical static timing analysis (SSTA) tool. While mainstream designs can readily take advantage of the PrimeTime advanced OCV solution, the PrimeTime VX solution provides further benefits for high-performance designs targeting advanced process technology nodes.
"The industry has welcomed PrimeTime's advanced OCV capability based on ease of adoption and effectiveness in accurately modeling on-chip variations," said Ahsan Bootehsaz, vice president of Research and Development, Synopsys Implementation Group. "By closely collaborating with leading semiconductor companies such as Renesas, we continue to bring innovative features to PrimeTime to help companies address their immediate design challenges, significantly boosting their designers' productivity."
About Synopsys
Synopsys, Inc. is the world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, software-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.
MOUNTAIN VIEW, Calif. -- April 14, 2009 -- Synopsys, Inc. , a world leader in software and IP for semiconductor design and manufacturing, today announced that Renesas Technology Corp. has deployed Synopsys' PrimeTime® advanced on-chip variation (OCV) capability to help accelerate timing closure for 65-nanometer (nm) and below system-on-chip (SoC) designs. PrimeTime advanced OCV analysis is an efficient, easy-to-adopt solution that employs adaptive derating to accurately account for random and systematic process variations across an integrated circuit (IC). This evolutionary approach brings the margin reduction benefits of variation-aware modeling to a broader range of customers and process technologies by eliminating the need to change libraries or significantly modify design flows. PrimeTime advanced OCV has been correlated to silicon at leading semiconductor companies including Renesas, qualified and recommended by the STARC Japanese semiconductor consortium, and is part of the stage-based on-chip variation solution in the TSMC Reference Flow 9.0.
"During a recent 45-nanometer tapeout, using the PrimeTime advanced OCV feature helped us achieve a 5X reduction in the number of timing violations we needed to analyze and fix, saving us a significant amount of schedule time," said Hitoshi Sugihara, department manager of the DFM & Digital EDA Technology Development Dept., Design Technology Div., Renesas Technology. "We collaborated with Synopsys early in the development of this methodology to ensure it was easy to deploy, and have confirmed its signoff accuracy versus both HSPICE Monte-Carlo (or statistical) simulation and actual silicon. The PrimeTime advanced OCV capability is now deployed as a standard part of our timing signoff flows at 65 nanometers and below."
Synopsys' PrimeTime advanced OCV technology provides more finely-tuned design margins in timing analysis by incorporating logic-depth information to determine path-specific and cell-specific margin values. Using simple derate tables to complement the global derate methodology that has been used for many years to account for on-chip variation allows PrimeTime customers to take advantage of the more finely-tuned design margins with minimal changes to existing timing signoff scripts. The PrimeTime advanced OCV capability is part of a comprehensive set of variation-aware design solutions offered by Synopsys that also includes the PrimeTime VX statistical static timing analysis (SSTA) tool. While mainstream designs can readily take advantage of the PrimeTime advanced OCV solution, the PrimeTime VX solution provides further benefits for high-performance designs targeting advanced process technology nodes.
"The industry has welcomed PrimeTime's advanced OCV capability based on ease of adoption and effectiveness in accurately modeling on-chip variations," said Ahsan Bootehsaz, vice president of Research and Development, Synopsys Implementation Group. "By closely collaborating with leading semiconductor companies such as Renesas, we continue to bring innovative features to PrimeTime to help companies address their immediate design challenges, significantly boosting their designers' productivity."
About Synopsys
Synopsys, Inc. is the world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, software-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.
|
||||||
Synopsys, Inc. Hot IP
Synopsys, Inc. Hot Verification IP
Related News
- Renesas Adopts Cadence Interconnect Workbench to Accelerate Performance Analysis and Verification of On-Chip Interconnect
- Synopsys' Fusion Compiler Enables Renesas to Accelerate Delivery of Next-Generation Automotive Designs
- Synopsys' PrimeTime Speeds Timing and Power Closure for Complex SoC and IoT Designs
- Synopsys' PrimeTime ADV Achieves Rapid Adoption for Fastest Timing Closure
- HiSilicon Chooses Synopsys' PrimeTime ADV for Faster Timing Closure
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models
Most Popular
|
E-mail This Article | 
|
|
Printer-Friendly Page |