English
Jasper, AMD Ink Long-Term Formal Verification Deal
JasperGold® now used in AMD design centers worldwide to reduce design risk and meet delivery schedules
Mountain View, Calif. – April 28, 2009 – Jasper Design Automation today announced it has signed a long-term agreement with AMD (NYSE: AMD) to place JasperGold formal verification technology in AMD design centers worldwide.
“We chose Jasper formal due to the level of their technology, methodology and support,” said Paul Tobin, Director of AMD's Verification Center of Expertise. “Jasper solutions help AMD to improve quality and reduce schedule risk. Jasper is now broadly accessible to multiple processor and graphics projects.”
AMD’s work with JasperGold exemplifies Jasper’s “Targeted ROI” philosophy, solving customers’ most critical design challenges in ways that also speed time to market, reduce overhead, and mitigate risk.
Tobin cited a recent example involving a complex, next-generation multi-core processor design. Designers wanted to prove that resource starvation would never occur in a new logic design; high-level analysis for which simulation alone is often insufficient. Using JasperGold’s unique interactive proof and liveness property capabilities, AMD was able to prove very early that this would not occur, saving extensive simulation time and gaining confidence in the extensive proof that formal verification can provide.
“Formal verification helps in the discovery of subtle RTL issues which are difficult or even impossible to detect in simulation,” Tobin added. “We strive to thoroughly verify critical logic in these complex designs to ensure discrepancies never have an impact on silicon, and Jasper helps us towards achieving that goal.”
About Jasper Design Automation
Jasper delivers industry-leading EDA software solutions for semiconductor design, verification, and reuse, based on the state-of-the-art formal technology. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics, with over 100 successful chip deployments. Jasper, headquartered in Mountain View, California, is privately held, with offices and distributors in North America, South America, Europe, and Japan. Visit www.jasper-da.com for Targeted ROI: reducing risks; increasing design, verification and reuse productivity; and accelerating time to market.
Mountain View, Calif. – April 28, 2009 – Jasper Design Automation today announced it has signed a long-term agreement with AMD (NYSE: AMD) to place JasperGold formal verification technology in AMD design centers worldwide.
“We chose Jasper formal due to the level of their technology, methodology and support,” said Paul Tobin, Director of AMD's Verification Center of Expertise. “Jasper solutions help AMD to improve quality and reduce schedule risk. Jasper is now broadly accessible to multiple processor and graphics projects.”
AMD’s work with JasperGold exemplifies Jasper’s “Targeted ROI” philosophy, solving customers’ most critical design challenges in ways that also speed time to market, reduce overhead, and mitigate risk.
Tobin cited a recent example involving a complex, next-generation multi-core processor design. Designers wanted to prove that resource starvation would never occur in a new logic design; high-level analysis for which simulation alone is often insufficient. Using JasperGold’s unique interactive proof and liveness property capabilities, AMD was able to prove very early that this would not occur, saving extensive simulation time and gaining confidence in the extensive proof that formal verification can provide.
“Formal verification helps in the discovery of subtle RTL issues which are difficult or even impossible to detect in simulation,” Tobin added. “We strive to thoroughly verify critical logic in these complex designs to ensure discrepancies never have an impact on silicon, and Jasper helps us towards achieving that goal.”
About Jasper Design Automation
Jasper delivers industry-leading EDA software solutions for semiconductor design, verification, and reuse, based on the state-of-the-art formal technology. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics, with over 100 successful chip deployments. Jasper, headquartered in Mountain View, California, is privately held, with offices and distributors in North America, South America, Europe, and Japan. Visit www.jasper-da.com for Targeted ROI: reducing risks; increasing design, verification and reuse productivity; and accelerating time to market.
|
||||||
Related News
- Tieto Signs Long-Term Agreement to Deploy OneSpin Solutions' Formal Assertion-Based Verification Solution
- Jasper Launches Security Path Verification App - Industry's First Formal Solution for Detecting Security Vulnerabilities in SoC Designs
- Jasper and Duolog Partner to Combine SoC Integration with Formal Verification
- Jasper Makes Formal Verification Power-Aware with a New Low Power App for Verification of SOCs with Multiple Power Domains
- OneSpin Solutions' Formal Verification Software Enables Maxim Integrated to Identify SoC Design Issues Early in the Project Cycle
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |