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Sarance Announces Availability of Complete Connectivity Solutions for Netronome's Network Flow Processors
Sarance’s Interlaken Intellectual Property products accelerate design and development of next generation networking equipment
Ottawa Canada -- May 27, 2009 -- Sarance Technologies, the leading supplier of high speed interconnect Intellectual Property (IP) technology, announced today the immediate availability of a complete connectivity solution for Netronome’s NFP-32xx family of Network Flow Processors™. The solution uses Sarance’s Interlaken IP Core (IIPC) products targeted for Field Programmable Gate Arrays (FPGAs) and provides a risk free solution for system developers using the NFP.
“Interlaken has become the industry standard for chip-to-chip connectivity, and Netronome is one of a growing number of fab-less semiconductor companies and networking OEMs that have licensed Sarance’s Interlaken Core to implement this function” said Farhad Shafai, Vice President of R&D at Sarance Technologies. “To facilitate the design of systems using the NFP, we are releasing an NFP compatible FPGA IIPC product that gurantees interoperability and provides a risk-free path for system developers to take advantage of what the NFP has to offer.”
"Netronome's Network Flow Processors are the first to include support for Interlaken," said Jim Finnegan, sr. vice president of silicon engineering at Netronome. "In addition to reducing our development complexity and cost, using Sarance's Interlaken Core ensures that the NFP interface is interoperable with a wide range of ASSP and ASICs coming to market shortly."
An FPGA based IIPC compatible with the NFP is available as a soft core for Virtex®-5 LXT, FXT and TXT FPGAs. The IIPC is also available for ASIC implementations. It has been implemented and validated in 65nm and 40nm process technologies. The IP is delivered as a netlist targeted for the specific FPGA architecture, or as RTL code that can be implemented in any ASIC process technology.
About Sarance Technologies:
Sarance Technologies is a leading supplier of ASIC and FPGA IP cores targeted at the packet processing space. The cores include MAC, PCS, Interlaken, packet classification and traffic management IP. To complement its IP offerings, Sarance offers a full range of design services intended to assist customers in meeting their time to market requirements. Sarance also provides full turnkey product development, custom IP development, and point solutions to assist customers in required areas. For more information, visit www.sarance.com.
Ottawa Canada -- May 27, 2009 -- Sarance Technologies, the leading supplier of high speed interconnect Intellectual Property (IP) technology, announced today the immediate availability of a complete connectivity solution for Netronome’s NFP-32xx family of Network Flow Processors™. The solution uses Sarance’s Interlaken IP Core (IIPC) products targeted for Field Programmable Gate Arrays (FPGAs) and provides a risk free solution for system developers using the NFP.
“Interlaken has become the industry standard for chip-to-chip connectivity, and Netronome is one of a growing number of fab-less semiconductor companies and networking OEMs that have licensed Sarance’s Interlaken Core to implement this function” said Farhad Shafai, Vice President of R&D at Sarance Technologies. “To facilitate the design of systems using the NFP, we are releasing an NFP compatible FPGA IIPC product that gurantees interoperability and provides a risk-free path for system developers to take advantage of what the NFP has to offer.”
"Netronome's Network Flow Processors are the first to include support for Interlaken," said Jim Finnegan, sr. vice president of silicon engineering at Netronome. "In addition to reducing our development complexity and cost, using Sarance's Interlaken Core ensures that the NFP interface is interoperable with a wide range of ASSP and ASICs coming to market shortly."
An FPGA based IIPC compatible with the NFP is available as a soft core for Virtex®-5 LXT, FXT and TXT FPGAs. The IIPC is also available for ASIC implementations. It has been implemented and validated in 65nm and 40nm process technologies. The IP is delivered as a netlist targeted for the specific FPGA architecture, or as RTL code that can be implemented in any ASIC process technology.
About Sarance Technologies:
Sarance Technologies is a leading supplier of ASIC and FPGA IP cores targeted at the packet processing space. The cores include MAC, PCS, Interlaken, packet classification and traffic management IP. To complement its IP offerings, Sarance offers a full range of design services intended to assist customers in meeting their time to market requirements. Sarance also provides full turnkey product development, custom IP development, and point solutions to assist customers in required areas. For more information, visit www.sarance.com.
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