English
eInfochips announces DDR2 SDRAM SystemVerilog & VMM based Memory Model Generator Tool
GUI based tool targeted to reduce verification time and maximize memory coverage
Ahmedabad -- June 2, 2009 -- eInfochips, Inc., a leading IP driven ASIC/FPGA/SoC, Embedded Systems & Software design services company today announced the availability of DDR2 SDRAM SystemVerilog VMM (Verification Methodology Manual) based Memory Model Generator. This HVL based tool is an integrated solution to generate behavioral models for all leading memory vendors such as Micron®, Samsung®, Hynix® & Elpida® thereby shortening verification time & maximizing memory coverage.
“We are very pleased to announce the DDR2 SDRAM SystemVerilog & VMM based behavioral memory model generator tool that offers high-quality simulation models and verification environments,” states Nirav Shah, Director of Marketing at eInfochips. “We always look for solutions that add value to the overall development and benefits industry. This tool will be exceptionally beneficial to ASIC/Chip/SoC level verification teams and memory controller IP developers”.
With eInfochips’ DDR2 SDRAM model generator, it is possible to configure parameters of DDR2 SDRAM memory such as memory size, data width, clock rate, cycle time, CAS latency and data rate.
Key Features of Memory Generator Tool
The DDR2 SDRAM memory generator is a TCL/TK based tool that supports leading memory vendors like Micron®, Samsung®, Hynix® & Elpida® and preserves a large library of part numbers for each supported memory vendor. The tool can be operated in 2 modes – Typical Mode or Custom Mode. In the Typical Mode, a user may choose vendors and part numbers to generate the memory model. In the Custom Mode, a user may create customized behavioral model from scratch by configuring parameter of DDR2 SDRAM through the configuration selection algorithm (CSA).
Key Features of Generated Behavioral Models
The behavioral models are compliant to JEDEC standard JESD79 – 2D and ready to be plugged into Verification Environment. The models offer in-built coverage and can be configured to turn On/Off initialization, enable/disable DDR2 interface checkers and coverage.
Deliverables
Deliverables include completely verified SystemVerilog VMM based DDR2 SDRAM generator encrypted code, user guide and release notes.
For more information on this IP please visit: http://www.einfochips.com/services/asic/IP/DDR2-SDRAM-MemoryGenerator-SystemVerilog-VMM.php
Support & Availability
DDR2 SDRAM SystemVerilog VMM based memory generator tool is now available and comes with support. For pricing details write to us at sales@einfochips.com
Currently the tool supports DDR2 but is expandable to support DDR, DDR3, NAND Flash, NOR Flash, QDR, XDR.
About eInfochips
eInfochips is a leading IP driven design services company with the range of services & solutions in ASIC/Chip/SoC, Embedded System and Software. eInfochips’ Chip/ASIC group has capabilities spanning from ASIC/Chip design, verification, physical design, FPGA design & prototyping and IP Cores development and integration. eInfochips has contributed to over 130+ designs in automotive, consumer, semiconductor, avionics, networking/communication, video and security/surveillance industries through its wide array of RTL to GDS II services and solutions. For more information, go to www.einfochips.com
Ahmedabad -- June 2, 2009 -- eInfochips, Inc., a leading IP driven ASIC/FPGA/SoC, Embedded Systems & Software design services company today announced the availability of DDR2 SDRAM SystemVerilog VMM (Verification Methodology Manual) based Memory Model Generator. This HVL based tool is an integrated solution to generate behavioral models for all leading memory vendors such as Micron®, Samsung®, Hynix® & Elpida® thereby shortening verification time & maximizing memory coverage.
“We are very pleased to announce the DDR2 SDRAM SystemVerilog & VMM based behavioral memory model generator tool that offers high-quality simulation models and verification environments,” states Nirav Shah, Director of Marketing at eInfochips. “We always look for solutions that add value to the overall development and benefits industry. This tool will be exceptionally beneficial to ASIC/Chip/SoC level verification teams and memory controller IP developers”.
With eInfochips’ DDR2 SDRAM model generator, it is possible to configure parameters of DDR2 SDRAM memory such as memory size, data width, clock rate, cycle time, CAS latency and data rate.
Key Features of Memory Generator Tool
The DDR2 SDRAM memory generator is a TCL/TK based tool that supports leading memory vendors like Micron®, Samsung®, Hynix® & Elpida® and preserves a large library of part numbers for each supported memory vendor. The tool can be operated in 2 modes – Typical Mode or Custom Mode. In the Typical Mode, a user may choose vendors and part numbers to generate the memory model. In the Custom Mode, a user may create customized behavioral model from scratch by configuring parameter of DDR2 SDRAM through the configuration selection algorithm (CSA).
Key Features of Generated Behavioral Models
The behavioral models are compliant to JEDEC standard JESD79 – 2D and ready to be plugged into Verification Environment. The models offer in-built coverage and can be configured to turn On/Off initialization, enable/disable DDR2 interface checkers and coverage.
Deliverables
Deliverables include completely verified SystemVerilog VMM based DDR2 SDRAM generator encrypted code, user guide and release notes.
For more information on this IP please visit: http://www.einfochips.com/services/asic/IP/DDR2-SDRAM-MemoryGenerator-SystemVerilog-VMM.php
Support & Availability
DDR2 SDRAM SystemVerilog VMM based memory generator tool is now available and comes with support. For pricing details write to us at sales@einfochips.com
Currently the tool supports DDR2 but is expandable to support DDR, DDR3, NAND Flash, NOR Flash, QDR, XDR.
About eInfochips
eInfochips is a leading IP driven design services company with the range of services & solutions in ASIC/Chip/SoC, Embedded System and Software. eInfochips’ Chip/ASIC group has capabilities spanning from ASIC/Chip design, verification, physical design, FPGA design & prototyping and IP Cores development and integration. eInfochips has contributed to over 130+ designs in automotive, consumer, semiconductor, avionics, networking/communication, video and security/surveillance industries through its wide array of RTL to GDS II services and solutions. For more information, go to www.einfochips.com
|
||||||
Related News
- SystemVerilog FrameWorks VMM Template Generator Upgraded for VMM 1.1
- Paradigm Works Announces VMM 1.0 enhancements to its SystemVerilog FrameWorks VMM Template Generator software
- eInfochips announces DDR2 SDRAM verification IP and Reed Solomon Encoder design IP
- CAST Expands Memory Controller Line with IP Core for DDR2 SDRAM Devices
- Synopsys to Release a Complete, Single Vendor Interface IP for High-Performance DDR2 SDRAM Memory Subsystems
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models
Most Popular
|
E-mail This Article | 
|
|
Printer-Friendly Page |