DeFacTo Demonstrates to TESSOLVE the Effectiveness of its RTL Testability Sign-off Solution
“Implementing complete testability at RTL level, including SCAN enables us to detect key testability issues and improve coverage early in design phase. Our evaluation has proven that the HiDFT-Scan flow helps detecting major testability problems at RTL with a very good accuracy, close to 0.5% in comparison to a gate-level flow. HiDFT-Scan has robust set of Design Rule Checks and enables new RTL DFT verification capabilities. We expect to take advantage from this flow with our future customers to be much more proactive in our design flow”, said Chandra sekhar Gandu, DFT Manager, TESSOLVE.
“We are pleased that the RTL testability sign-off solution from DeFacTo has demonstrated to TESSOLVE a tangible added value in comparison to traditional DFT flows with a full independence from the synthesis process” said Chouki Aktouf, Founder & CEO of DeFacTo Technologies. “We look forward to extending our collaboration with TESSOLVE to help solving crucial DFT problems”.
About TESSOLVE
Tessolve is an independent engineering services company offering cutting edge solutions in DFT, Test Engineering, Test hardware development, Package Assembly and Failure Analysis. Based out of Bangalore, India, Tessolve has a team of 400+ people specialising in the above mentioned service offerings. With its state of the art facility, Tessolve is equipped with the most sophisticated test systems and dedicated engineering team to develop test solutions for RF, advanced mixed signal, memory and digital devices.
About DeFacTo Technologies
DeFacTo Technologies is a leading provider of Design-for-Test solutions at RTL. DeFacTo solutions enable designers to complete planning, analysis and implementation of integrated circuit test logic before synthesis by delivering a high quality suite of tools working at RTL. DeFacTo’s R&D is based in Grenoble (France) with a sales office is Palo Alto.
|
Related News
- Real Intent and Calypto Partner to Offer Best-in-Class Integrated Tool Flow for RTL Power Optimization and Sign-Off
- DeFacTo Technologies Announces PLX Technology Adopts HiDFT-SIGNOFF Solution for RTL Testability
- DeFacTo Unveils New Design for Test Product that Eliminates Need for Gate-level Scan; Creates Industry's First High-level DFT Sign-off Methodology
- Real Intent Joins DARPA Toolbox Initiative to Provide Mil/Aero/Defense Grade Static Sign-Off
- CEO interview: Minima's Tuomas Hollman on why static timing sign-off is over
Breaking News
- JEDEC® and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard: Advancing Bandwidth, Efficiency, and Capacity for AI and HPC
- BrainChip Gives the Edge to Search and Rescue Operations
- ASML targeted in latest round of US tariffs
- Andes Technology Celebrates 20 Years with New Logo and Headquarters Expansion
- Creonic Unveils Bold Rebrand to Drive Innovation in Communication Technologies
Most Popular
- Cadence to Acquire Arm Artisan Foundation IP Business
- AMD Achieves First TSMC N2 Product Silicon Milestone
- Why Do Hyperscalers Design Their Own CPUs?
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- New TSN-MACsec IP core for secure data transmission in 5G/6G communication networks
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |