English
Lattice Announces Updates and Enhancements to its FPGA Design Tool Suite
Design Tools Now Include Updated Support for the Mid-range LatticeECP3 and Non-volatile LatticeXP2 FPGA Families
HILLSBORO, OR - JUNE 15, 2009 - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of Service Pack 2 for Version 7.2 of its ispLEVER® FPGA design tool suite. SP2 is a particularly important update for users of LatticeECP3™ devices, and also includes support for new LatticeXP2™ devices.
"Service Pack 2 further expands the breadth of Lattice product design support. More specifically, this important update allows users of ECP3-70 and ECP-95 devices to design with even greater confidence that the board-level behavior of their design, such as simultaneous switching output noise (SSO), power and timing, will match what the tools report," said Mike Kendrick, Lattice's Manager of Software Product Planning. "SP2 also boosts DSP application performance in the LatticeECP3 devices."
Updated Support for the LatticeECP3 FPGA Family
Design support for the LatticeECP3 FPGA Family was first made available in the ispLEVER 7.2 SP1 design tool suite. Service Pack 2 updates the device values to production characterized silicon for the LatticeECP3-70 and ECP3-95 devices. With SP2, static timing analysis, power and SSO will report results that even more accurately reflect the behavior of the actual production device. Moreover, PCS/SERDES calibration settings used for the supported IO protocols have been tuned to provide more robust behavior. The sysDSP™ block support also has been enhanced to include higher performance modes of primitive blocks targeted at specific applications, such as FIR filters, decimators, interpolators, matrix multiplication and video applications. These modes are made possible by the enhanced cascade support in the LatticeECP3 devices' sysDSP architecture.
Support for New LatticeXP2 Products
Service Pack 2 also supports the recently announced industrial temperature qualified, non-volatile LatticeXP2 devices that are available now in low-cost, small-footprint BGA or QFP packaging.
About the ispLEVER Design Tool Suite
The ispLEVER design tool suite is the flagship design environment for the latest Lattice FPGA products. It provides a complete set of powerful tools for all design tasks, including project management, IP integration, design planning, place and route, in-system logic analysis and more. The ispLEVER tool suite is provided on CD-ROM and DVD for Windows, UNIX or Linux platforms. Synopsys' Synplify Pro advanced FPGA synthesis is included for all operating systems supported, and Aldec's Active-HDL Lattice Edition simulator is included for Windows.
Third Party Tool Support
In addition to the tool support for Lattice devices provided by the OEM versions of Synplify Pro and Active-HDL, which are included in the ispLEVER tool suite, Lattice devices are also supported by the full versions of Synopsys Synplify Pro and Aldec Active-HDL. Mentor Graphics ModelSim SE and Precision RTL synthesis also support the latest Lattice devices, such as the LatticeECP3 family. Precision RTL synthesis support for LatticeECP3 devices requires an update that is available from the Mentor Graphics website.
Pricing and Availability
The ispLEVER 7.2 Service Pack 2 tool suite for Windows, LINUX and UNIX users is available immediately without charge for customers with active design tool maintenance contracts. Pricing for the full ispLEVER design tool suite starts at $1,295 for the Windows version.
About Lattice Semiconductor
Lattice is the source for innovative FPGA, PLD and Mixed Signal programmable logic solutions. For more information, visit www.latticesemi.com
HILLSBORO, OR - JUNE 15, 2009 - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of Service Pack 2 for Version 7.2 of its ispLEVER® FPGA design tool suite. SP2 is a particularly important update for users of LatticeECP3™ devices, and also includes support for new LatticeXP2™ devices.
"Service Pack 2 further expands the breadth of Lattice product design support. More specifically, this important update allows users of ECP3-70 and ECP-95 devices to design with even greater confidence that the board-level behavior of their design, such as simultaneous switching output noise (SSO), power and timing, will match what the tools report," said Mike Kendrick, Lattice's Manager of Software Product Planning. "SP2 also boosts DSP application performance in the LatticeECP3 devices."
Updated Support for the LatticeECP3 FPGA Family
Design support for the LatticeECP3 FPGA Family was first made available in the ispLEVER 7.2 SP1 design tool suite. Service Pack 2 updates the device values to production characterized silicon for the LatticeECP3-70 and ECP3-95 devices. With SP2, static timing analysis, power and SSO will report results that even more accurately reflect the behavior of the actual production device. Moreover, PCS/SERDES calibration settings used for the supported IO protocols have been tuned to provide more robust behavior. The sysDSP™ block support also has been enhanced to include higher performance modes of primitive blocks targeted at specific applications, such as FIR filters, decimators, interpolators, matrix multiplication and video applications. These modes are made possible by the enhanced cascade support in the LatticeECP3 devices' sysDSP architecture.
Support for New LatticeXP2 Products
Service Pack 2 also supports the recently announced industrial temperature qualified, non-volatile LatticeXP2 devices that are available now in low-cost, small-footprint BGA or QFP packaging.
About the ispLEVER Design Tool Suite
The ispLEVER design tool suite is the flagship design environment for the latest Lattice FPGA products. It provides a complete set of powerful tools for all design tasks, including project management, IP integration, design planning, place and route, in-system logic analysis and more. The ispLEVER tool suite is provided on CD-ROM and DVD for Windows, UNIX or Linux platforms. Synopsys' Synplify Pro advanced FPGA synthesis is included for all operating systems supported, and Aldec's Active-HDL Lattice Edition simulator is included for Windows.
Third Party Tool Support
In addition to the tool support for Lattice devices provided by the OEM versions of Synplify Pro and Active-HDL, which are included in the ispLEVER tool suite, Lattice devices are also supported by the full versions of Synopsys Synplify Pro and Aldec Active-HDL. Mentor Graphics ModelSim SE and Precision RTL synthesis also support the latest Lattice devices, such as the LatticeECP3 family. Precision RTL synthesis support for LatticeECP3 devices requires an update that is available from the Mentor Graphics website.
Pricing and Availability
The ispLEVER 7.2 Service Pack 2 tool suite for Windows, LINUX and UNIX users is available immediately without charge for customers with active design tool maintenance contracts. Pricing for the full ispLEVER design tool suite starts at $1,295 for the Windows version.
About Lattice Semiconductor
Lattice is the source for innovative FPGA, PLD and Mixed Signal programmable logic solutions. For more information, visit www.latticesemi.com
|
||||||
Related News
- Lattice Announces Updates and Enhancements to Its FPGA Design Tool Suite
- Lattice Announces Update to ispLEVER FPGA Design Tool Suite
- New Lattice FPGA Design Tool Suite Includes Advanced Support for High Performance DDR Interfaces
- Lattice's ispLEVER 7.2 FPGA Design Tool Suite Continues to Elevate Designers' Productivity
- Lattice Announces ispLEVER 7.1 Service Pack 1 FPGA Design Tool Suite
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |