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Northwest links SDRAM controller, Altera PCI core
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Northwest links SDRAM controller, Altera PCI core
By Michael Santarini, EE Times
April 19, 1999 (10:05 a.m. EST)
URL: http://www.eetimes.com/story/OEG19990419S0003
Building on its strategy to bring a workable 64-bit, 66-MHz PCI core to programmable-logic users, Altera Corp. (San Jose, Calif.) and Northwest Logic Design (Beaverton, Ore.) have unveiled an SDRAM controller with over-100-MHz performance that can be seamlessly integrated with Altera's new PCI offering, the companies said.
The companies said the combined solution, which uses 3,500 logic cells in the Flex 10KE family of CPLDs, can quicken integration into high-speed, memory-intensive designs in programmable logic.
According to the companies, the integration was made possible when Northwest Logic Design, a new Altera Megafunction Partner Program member, developed an SDRAM controller core that can achieve greater than 100-MHz performance in Altera's Flex 10KE family of PLDs.
The solution makes the controller suitable for a variety of applications, including embedded PCI and PowerPC.
The first interface module aims at embed ded-processing apps and connects to the Motorola PowerPC 60x and 750 processors. The second interface module adds internal FIFOs and control logic so that the SDRAM can be used as a high-speed video-frame buffer. This application is for HDTV or SXGA-VGA digital-video buffering.
The third interface module provides a seamless connection to the Altera 64-bit, 66-MHz PCI/C Megafunction core. An internal FIFO is included to minimize PCI wait states and maximize SDRAM access efficiency.
Northwest Logic Design's new SDRAM controller core, including encrypted net-list form and target .acf files, is available now for $4,995.
To obtain the SDRAM controller with an interface to Altera's PCI/C core, customers must ask for the PCI Interface module. Customers can evaluate Northwest Logic Design's core free prior to licensing via Altera's OpenCore program at www.altera.com.
Alternatively, the SDRAM controller is available in VHDL or Verilog or Verilog source code directly from Northwest Logic Design at www.nwlogic.com.
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Proving it can bend in the ever-changing winds of the ASIC library business, standard-cell library vendor Virtual Silicon Inc. has announced it is expanding its product line beyond portable libraries and will offer TSMC customers process-specific libraries.
Virtual Silicon's first foundry-specific libraries include memory compilers, standard cells and I/O pads for TSMC's 0.25-micron process technology.
According to Virtual Silicon, the company has delivered TSMC-specific 0.25-micron libraries to Oak Technology, Standard Microsystems and other semiconductor vendors.
The company said it is using its test-chip program to verify its libraries on TSMC's 0.25-process technology, and the results are available in a series of process-correlation reports covering timing verification, high-density layout-technique verification, I/O performance and reliability.
V irtual Silicon said it taped out a 0.18-micron TSMC-specific test chip in February and expects to see the results in mid-April. Visit www.virtual-silicon.com.
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