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Satin IP Technologies Helps STMicroelectronics Achieve IP Design Quality Closure
Companies to jointly present at DAC 2009 on enabling IP quality closure
MONTPELLIER, France – July 13, 2009 – Satin IP Technologies, the company that delivers design quality closure with fast return on investment, has been working with the Home Entertainment and Display (HED) product group of STMicroelectronics on how to monitor and improve the quality of their internally developed semiconductor intellectual property (IP) blocks.
With systems-on-chip (SoCs) now comprised of more than 50 IP blocks, the quality of IP deliveries is a key factor to ensure risk-free integration and predictable schedules. To help improve IP quality, STMicroelectronics has defined design standards over time, along with a design flow to implement them. However, with the growing complexity of both the IP blocks and the design flow, the quantity of data to be monitored had become too big to authorize continuous and accurate quality monitoring with ad hoc techniques. ST’s HED product group now uses Satin IP’s VIP Lane® to extract key data from their IP design flow and to achieve on-the-fly quality monitoring during the development cycle. VIP Lane also provides automated production of IP integration documents and easier supervision of all the IP blocks of a given SoC.
“VIP Lane adds new capabilities to the quality design flow that HED has been working on for years,” said François Rémond, CAD & design methodology director at ST’s HED product group. “These enlarged capabilities lead to faster identification of quality metrics requiring special attention, better communication between IP and SoC design teams and measured savings on design time-to-integration.”
“ST has a long history of defining design practices and deploying tools for developing IP blocks that integrate smoothly. These practices and tools led to the definition of quality metrics that VIP Lane was able to automate to help ST with monitoring and deployment. And ST can maintain these metrics in the long term,” said Michel Tabusse, CEO of Satin IP Technologies.
In the User Track session at DAC 2009 on Wednesday, July 29th, from 1:30 – 3:00, Satin IP and ST’s HED product group will present information on how design quality closure applies to a family of IP blocks for the 55nm set-top-box SoC, and will outline the measured benefits.
About Satin IP Technologies
Committed to design quality closure with fast return on investment (ROI), Satin IP Technologies delivers software solutions for fact-based design quality monitoring. Working within customers' design flows, VIP Lane® turns customers' design practices for IP blocks or SoCs into a robust set of quality criteria and automates the implementation and documentation of design quality metrics at no extra cost in engineering time or resources. VIP Lane shortens time-to-market by delivering effective flow integration and on-the-fly quality monitoring at zero overhead to design teams. Satin IP is a privately-held company with headquarters in Montpellier, France. For more information, see www.satin-ip.com
MONTPELLIER, France – July 13, 2009 – Satin IP Technologies, the company that delivers design quality closure with fast return on investment, has been working with the Home Entertainment and Display (HED) product group of STMicroelectronics on how to monitor and improve the quality of their internally developed semiconductor intellectual property (IP) blocks.
With systems-on-chip (SoCs) now comprised of more than 50 IP blocks, the quality of IP deliveries is a key factor to ensure risk-free integration and predictable schedules. To help improve IP quality, STMicroelectronics has defined design standards over time, along with a design flow to implement them. However, with the growing complexity of both the IP blocks and the design flow, the quantity of data to be monitored had become too big to authorize continuous and accurate quality monitoring with ad hoc techniques. ST’s HED product group now uses Satin IP’s VIP Lane® to extract key data from their IP design flow and to achieve on-the-fly quality monitoring during the development cycle. VIP Lane also provides automated production of IP integration documents and easier supervision of all the IP blocks of a given SoC.
“VIP Lane adds new capabilities to the quality design flow that HED has been working on for years,” said François Rémond, CAD & design methodology director at ST’s HED product group. “These enlarged capabilities lead to faster identification of quality metrics requiring special attention, better communication between IP and SoC design teams and measured savings on design time-to-integration.”
“ST has a long history of defining design practices and deploying tools for developing IP blocks that integrate smoothly. These practices and tools led to the definition of quality metrics that VIP Lane was able to automate to help ST with monitoring and deployment. And ST can maintain these metrics in the long term,” said Michel Tabusse, CEO of Satin IP Technologies.
In the User Track session at DAC 2009 on Wednesday, July 29th, from 1:30 – 3:00, Satin IP and ST’s HED product group will present information on how design quality closure applies to a family of IP blocks for the 55nm set-top-box SoC, and will outline the measured benefits.
About Satin IP Technologies
Committed to design quality closure with fast return on investment (ROI), Satin IP Technologies delivers software solutions for fact-based design quality monitoring. Working within customers' design flows, VIP Lane® turns customers' design practices for IP blocks or SoCs into a robust set of quality criteria and automates the implementation and documentation of design quality metrics at no extra cost in engineering time or resources. VIP Lane shortens time-to-market by delivering effective flow integration and on-the-fly quality monitoring at zero overhead to design teams. Satin IP is a privately-held company with headquarters in Montpellier, France. For more information, see www.satin-ip.com
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