HDL Design House announces Serial Rapid IO soft IP core (HIP 3300)
HIP3300 IP Core Key Features:
- Conforms to the latest RapidIO Interconnect specification – Rev.2.0.1.
- AMBA 3 AXI ARM CPU host interface, for high performance on-chip communication.
- Supports multiple high speed lanes, (1x, 2x, 4x, 8x and 16x modes)
- Configurable modes of operation; 1.25 Gbaud/s, 2.5 Gbaud/s, 3.125 Gbaud/s, 5Gbaud/s, 6.25Gbaud/s transfer rates
- Internal multi-channel DMA controller that fully exploits AXI protocol features and thus supports highest available data throughput and back to back packets transmission.
- Configuration and Status Register File containing over 40 architectural registers providing total software control of IP core.
- Number of software maskable interrupt request signals.
- Full backward compatibility with RapidIO specification revision 1.3
- Provides roadmap to future RapidIO specification revisions.
- Physical Coding Sub-layer (PCS)
- 8B/10B Encoding and Decoding support
- Physical Medium Attachment (PMA)
- Error management extensions
- Clock and Data Recovery
- Lane Synchronization
- CRC Generation and Checking
- Packet/Control Symbol Assembly and Deassembly
- Supports all RapidIO packet sizes
- Long control symbols
- Scrambler/Descrambler
- Idle2 sequence
- Idle2 CS
- RT Virtual channels
- CT Virtual channels
HDL DH has been member of RapidIO Trade Association since February 2008.
HDL DH offers a number of foundry-independent IP cores available for embedded, networking, communications, and computing applications. HDL DH provides, as part of the IP licensing package, an extensive set of documentation and customer support capabilities. The IP package consists of Verilog RTL code and detailed design documentations. HDL DH also offers a suite of design services for customization and integration of the IP cores into each customer’s ICs and FPGAs.
HDL DH also provides a variety of verification solutions including Serial RapidIO protocols. The Serial RapidIO verification solution may be part of HIP 3300 soft IP core delivery, depending on customer requirements.
Upon request, new customers may use all HDL DH IP cores free of charge during the evaluation period.
The HIP 3300 IP core will be available in Q3/2009.
If you are interested in finding out more about the HIP 3300 IP core, please visit www.hdl-dh.com or download the datasheet from the following link: http://www.hdl-dh.com/ipproducts.html
About HDL Design House:
HDL Design House delivers leading-edge design and verification services and products in numerous areas of SoC and complex FPGA designs. The company develops IP cores and provides complete design and verification services for complex SoC projects. The company also delivers component (VITAL) models for major SoC product developers. Dedicated to fulfilling each customer's unique requirements, HDL Design House has established a reputation as a reliable partner with high-quality products and services, flexible licensing models, competitive pricing and responsible technical support. The company enables customers to concentrate on system-level work and be confident that the various system components have been fully and reliably engineered and tested.
Founded in 2001, HDL Design House has 62 employees in two design centers – in Belgrade and Cuprija (Serbia). The company was awarded ISO 9001:2000 and ISO 27001:2005 certifications in December 2006 and has achieved certifications from Direct Assessment Services (DAS), thereby meeting United Kingdom Accreditation Service (UKAS) regulatory requirements. With ISO 27001:2005 certification, the highest certification standard for information security available, HDL Design House becomes the first company in Serbia to comply with this standard. In 2006 the company was awarded the SME Exporter of the Year by Serbia Investment and Export Promotion Agency (SIEPA).
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