English
Lattice Announces Updated, More Accessible CPLD Design Tools
ispLEVER Classic Version 1.3 Design Tools Feature Updated CPLD Support and Faster, Modular Installation
HILLSBORO, OR - AUGUST 3, 2009 - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of Version 1.3 of its ispLEVER® Classic design tool suite. Version 1.3 includes updated support for Lattice CPLDs (Complex Programmable Logic Devices), including the widely popular ispMACH® 4000 device family. Designers can quickly download, for free, ispLEVER Classic for Windows, as well as optional Synopsys Synplify logic synthesis and Aldec Active-HDL simulator modules from: www.latticesemi.com/products/designsoftware/isplever/ispleverclassic. The ispLEVER Classic software download has been segmented into modules to make download and installation faster and more convenient.
The ispLEVER Classic 1.3 software also includes updated ordering part number designations for GAL® 22V10 lead free QFNS package devices. To further support designers who maintain mature systems with discontinued Lattice devices, ispLEVER Classic1.3 software now includes the "Obsolete Pack," which enables additional device support within the design tools. To enable the pack, users simply check the "Show Obsolete Devices" option within the new Project Wizard feature of the Project Navigator application.
About the ispLEVER Classic Design Tool Suite
ispLEVER Classic is the design environment for Lattice CPLDs and mature programmable products. It can be used to take a Lattice device design completely through the design process, from concept to device JEDEC or bitstream programming file output. The ispLEVER Classic for Windows tool suite is a free download from the Lattice website at www.latticesemi.com/products/designsoftware/isplever/ispleverclassic. The ispLEVER Classic software is also distributed with the ispLEVER/Pro tool suite, which is provided on both CD-ROM and DVD.
Third Party Tool Support
In addition to the tool support for Lattice devices provided by the downloadable versions of Synopsys Synplify for Lattice and Active-HDL Lattice Web Edition, Lattice devices are also supported by the full versions of Synopsys Synplify and Aldec Active-HDL.
Pricing and Availability
The ispLEVER Classic 1.3 tool suite for Windows users is available immediately for free.
About Lattice Semiconductor
Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. For more information, visit www.latticesemi.com
HILLSBORO, OR - AUGUST 3, 2009 - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of Version 1.3 of its ispLEVER® Classic design tool suite. Version 1.3 includes updated support for Lattice CPLDs (Complex Programmable Logic Devices), including the widely popular ispMACH® 4000 device family. Designers can quickly download, for free, ispLEVER Classic for Windows, as well as optional Synopsys Synplify logic synthesis and Aldec Active-HDL simulator modules from: www.latticesemi.com/products/designsoftware/isplever/ispleverclassic. The ispLEVER Classic software download has been segmented into modules to make download and installation faster and more convenient.
The ispLEVER Classic 1.3 software also includes updated ordering part number designations for GAL® 22V10 lead free QFNS package devices. To further support designers who maintain mature systems with discontinued Lattice devices, ispLEVER Classic1.3 software now includes the "Obsolete Pack," which enables additional device support within the design tools. To enable the pack, users simply check the "Show Obsolete Devices" option within the new Project Wizard feature of the Project Navigator application.
About the ispLEVER Classic Design Tool Suite
ispLEVER Classic is the design environment for Lattice CPLDs and mature programmable products. It can be used to take a Lattice device design completely through the design process, from concept to device JEDEC or bitstream programming file output. The ispLEVER Classic for Windows tool suite is a free download from the Lattice website at www.latticesemi.com/products/designsoftware/isplever/ispleverclassic. The ispLEVER Classic software is also distributed with the ispLEVER/Pro tool suite, which is provided on both CD-ROM and DVD.
Third Party Tool Support
In addition to the tool support for Lattice devices provided by the downloadable versions of Synopsys Synplify for Lattice and Active-HDL Lattice Web Edition, Lattice devices are also supported by the full versions of Synopsys Synplify and Aldec Active-HDL.
Pricing and Availability
The ispLEVER Classic 1.3 tool suite for Windows users is available immediately for free.
About Lattice Semiconductor
Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. For more information, visit www.latticesemi.com
|
||||||
Related News
- Lattice Announces Improved Synthesis and Power Optimization in CPLD Design Tools
- Lattice ispLEVER Classic Design Tools Now Support New CPLD Family
- IAR Systems enables secure code with updated MISRA C compliance in leading development tools
- Lattice Semiconductor and Synopsys Renew Partnership on FPGA Synthesis Tools
- Radiant 1.1 Lattice FPGA Design Tools Release Accelerates Design Reuse
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |