De Geus IDs trouble spots for system-on-a-chip designs

This past decade's boom in semiconductor technologies was paid for by the success of end products, most notably the PC, de Geus said, but the coming wave of "killer app" products, whether digital TVs and third-generation mobile phones, will require a similar boom in design tools, he said.

"Design has not kept up in complexity," de Geus said. "Design is the bottleneck to what potentially can be fabricated."

In addition, advances in semiconductor equipment and the success of pure-play foundries has p ut all chip companies on equal footing in terms of manufacturing, which is no longer an advantage or even a worthwhile pursuit for most semiconductor companies. "Design is clearly the next differentiator," de Geus said. "The challenge comes from only one thing — growth in complexity."

System-on-a-chip development, in particular, has encountered critical problem areas, all of which will require advances in design tools, de Geus said.

The first such area involves timing, specifically the inability to predict timing at high levels of design. Timing problems often can't be spotted until later in the design process, and at that point, any changes can create new critical paths and new timing problems, de Geus said. "A designer at Sun told me they had to go through 23 iterations between logic and layout to get the timing right," he said.

While a number of startups have tried tackling this problem with "glue" tools to correlate synthesis and place-and-route, Synopsys' answer is the rece ntly announced Chip Architect and its "physical synthesis" approach, which "glues together high-level design and physical design in the way that designers think," de Geus said.

Verification is the next bottleneck faced by designers, as it consumes up to 50 percent of a design's time. The reason, again, is complexity: if Moore's Law predicts that transistor density increases 10 times every six years, then the number of test vectors required increases 100 times, de Geus said. "Traditional simulation is running out of gas," he said.

One solution would be to move simulation to the highest level possible. Another would be to split the problem into timing verification and formal verification — an approach increasingly being discussed as formal verification matures.

Hand-in-hand with this kind of functional verification is the verification of timing, which de Geus identified as the third trouble spot. Physical effects at the deep-submicron level ar e causing oddities such as crosstalk and lack of signal integrity, which often aren't discovered until tapeout. While it's becoming easy to spot such problems, it's impossible to strike them out if they're proliferated all around the chip, de Geus said.

Ideally, such effects have to be intercepted directly by design tools during routing. In this vein, de Geus sees routing coming closer to deep-submicron analysis, much in the way that placement and synthesis are merged in Synopsys' physical synthesis concept.

Design reuse, largely accepted as a prerequisite for system-on-a-chip success, was the fourth problem cited by de Geus. "It implies a set of standards and a strict methodology," both of which remain incomplete, he said. One breakthrough along those lines was the Reuse Methodology Manual published jointly by Synopsys and Mentor Graphics Corp. and which is being followed in some IP circles.

"As IP gets reused multiple times, we do see increased return. The main thing, though, is the initial investment. It's not so much the money as the cost to the schedule," he said.

Finally, de Geus brought up the divergence of hardware and software during design, a problem to be solved by hardware-software coverification and ultimately by outright codesign. The trick here, he said, is to keep the two sides compatible with one another as the design progresses. Tools that will be released over the next few years should help that effort, he said.