English
Faraday Offers 55nm/ 65nm miniIO with around 40% Area-Saving and Robust ESD Performance
August 18, 2009 -- Faraday Technology Corporation (TAIEX: 3035) today announced the availability of its innovative miniIO™ at 55nm and 65nm. Compared with general IO pads, Faraday's miniIO™ reduces the chip area by up to 40% for a pad-limited design with 500 pins, while keeping the same programming IO functionality, and achieving robust ESD performance. Targeted for fabless design houses in multi-voltage applications (1.8V-3.3V), Faraday's miniIO™ has been silicon proven via complete functional verification.
The ultra fine pitch of Faraday's 55nm/ 65nm miniIO™ surpasses the average pad pitch rules (25um pad pitch in 2 row staggered). Supporting Tri-Tier Bonding and BOAC with a fine bonding pitch of 16-17um, these miniIO™ meet the demand for high-pin-counts that are common for tomorrow's sophisticated and complex SoC designs. In addition, Faraday's newly-launched 55nm/ 65nm miniIO™ provide slimmer power pads, input I/O buffers and output / bi-di I/O buffers with widths of only 17nm. Taking a chip with 500 pins as an example, the area of miniIO™ (6.38mm²) is less than those of a comparable chip with 35um (22.8mm²) and 25um (12.43mm²) pad pitches by 72% and 50% respectively.
"We are very proud to offer an IO cell solution which goes beyond the general pad pitch rules. Within half a year, Faraday has continuously launched a series of miniIO™ from 0.13um, 90nm, 65nm, and now 55nm," said Eliot Chen, Associate Vice President of RD at Faraday. "This was the culmination of Faraday's long involvement in IO development and relentless pursuit of customer satisfaction. As always, these cells are easily integrated and allow our customers the greatest flexibility in their designs," he added.
"The effective area-reduction of Faraday's miniIO™ enables the highly integrated chip at 55nm and 65nm advanced nodes to reduce chip costs substantially, especially in pad-limited designs," said Steve Wang, Chief Strategy Officer at Faraday. "We are now cooperating with customers who will apply the newly-launched ultra slim miniIO™ together with our high-evaluated 65nm/ 55nm miniLib™ and PowerSlash™. It is expected to bring a higher performance/cost value," he added.
Availability
Faraday's miniIO™ at 55nm and 65nm are now available, and can support BOAC.
About Faraday Technology Corporation
Faraday Technology Corporation is a leading fabless ASIC and silicon IP provider. The company's broad silicon IP portfolio includes Cell Library, Memory Compiler, ARM-compliant CPUs, DDRI/II/III, MPEG4, H.264, USB 2.0/3.0, 10/100 Ethernet, Serial ATA, and PCI Express. With 2008 revenue of US$ 149 million, Faraday is one of the largest fabless ASIC companies in the Asia-Pacific region, and it also has a significant presence in other world-wide markets. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. For more information, please visit : www.faraday-tech.com
The ultra fine pitch of Faraday's 55nm/ 65nm miniIO™ surpasses the average pad pitch rules (25um pad pitch in 2 row staggered). Supporting Tri-Tier Bonding and BOAC with a fine bonding pitch of 16-17um, these miniIO™ meet the demand for high-pin-counts that are common for tomorrow's sophisticated and complex SoC designs. In addition, Faraday's newly-launched 55nm/ 65nm miniIO™ provide slimmer power pads, input I/O buffers and output / bi-di I/O buffers with widths of only 17nm. Taking a chip with 500 pins as an example, the area of miniIO™ (6.38mm²) is less than those of a comparable chip with 35um (22.8mm²) and 25um (12.43mm²) pad pitches by 72% and 50% respectively.
"We are very proud to offer an IO cell solution which goes beyond the general pad pitch rules. Within half a year, Faraday has continuously launched a series of miniIO™ from 0.13um, 90nm, 65nm, and now 55nm," said Eliot Chen, Associate Vice President of RD at Faraday. "This was the culmination of Faraday's long involvement in IO development and relentless pursuit of customer satisfaction. As always, these cells are easily integrated and allow our customers the greatest flexibility in their designs," he added.
"The effective area-reduction of Faraday's miniIO™ enables the highly integrated chip at 55nm and 65nm advanced nodes to reduce chip costs substantially, especially in pad-limited designs," said Steve Wang, Chief Strategy Officer at Faraday. "We are now cooperating with customers who will apply the newly-launched ultra slim miniIO™ together with our high-evaluated 65nm/ 55nm miniLib™ and PowerSlash™. It is expected to bring a higher performance/cost value," he added.
Availability
Faraday's miniIO™ at 55nm and 65nm are now available, and can support BOAC.
About Faraday Technology Corporation
Faraday Technology Corporation is a leading fabless ASIC and silicon IP provider. The company's broad silicon IP portfolio includes Cell Library, Memory Compiler, ARM-compliant CPUs, DDRI/II/III, MPEG4, H.264, USB 2.0/3.0, 10/100 Ethernet, Serial ATA, and PCI Express. With 2008 revenue of US$ 149 million, Faraday is one of the largest fabless ASIC companies in the Asia-Pacific region, and it also has a significant presence in other world-wide markets. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. For more information, please visit : www.faraday-tech.com
|
||||||
Faraday Technology Corp. Hot IP
Related News
- Faraday Offers 0.13um miniIO with around 40% Area-Saving and Robust ESD Performance
- Innopower Offers Industrial-leading Miniaturized Cell Library, the miniLib+ and miniIO+, in 130nm, 110nm, 65nm and 55nm Technologies
- Faraday Offers the Miniaturized Cell Library miniLib in both 90nm and 65nm
- Faraday Offers the First Memory Compiler in UMC 65nm LL Process
- Aragio Solutions Offers Suite of Programmable GPIO I/O Libraries Supporting 65nm Common Platform Technology Available for Chartered Customers
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |