UMC readies 0.18-micron capacity, cores

UMC's total 0.18-micron wafer capacity will increase to 18,000 wafers per month by the end of the year, and 0.18-micron will be the most cost-effective technology by this time next year for its foundry-service customers, said Ray Cisneros, a product manager at UMC USA here.

By the second half of 1999, the UMC Group plans to offer copper interconnects on five of the six metal layers, complementing the "low-k" fluorinated silicon dioxide being used as the interlevel dielectric.

UMC already has run wafers at the 0.18-micron design rule for Xilinx Inc. and S3 Inc., and the initial volume production will be at USIC, the Hsinchu, Taiwan, fab jointly owned by UMC, SanDisk and Xilinx. Last November, Xilinx and UMC developed the mask set for Xilinx's 0.18-micron-generation complex FPGAs, and initial results showed frequencies in the 1-GHz range. The Xilinx parts, and a graphics chip from S3, will serve as the process drivers for the new process.

To get ready for its mainstay foundry-service business, late last year UMC started a test-wafer run — called a Silicon Shuttle — with several prototype designs fabricated on the same wafer. Included on that shuttle were extraction models from Simplex Solutions Inc. that provide speed, parasitic and power information from the interconnect grid.

That first Silicon Shuttle will reach the wafer-out stage soon, and a second shuttle with 0.18-micron test chips and core will be launched in March.

Besides offering the ability to run test wafers at relatively little cost on the Silicon Shuttle, UMC also has developed a less costly means of accessing the IP cores that designers may need to complete 0.18-micron designs.

UMC has forged deals that allow its customers to use cores from Mentor Graphics Corp. and Artisan Components and obtain technical support, without requiring a direct license from those IP vendors. With technical support for the validated cores, design houses can attempt system-on-a-chip designs that might have been beyond their resources otherwise.

A spokesman for Mentor said UMC customers that want to use the Inventra library of more than 110 cores, for example, could work primarily with UMC. A simple agreement between Mentor and the UMC customer still would be required, but the goal is to keep the legal process as simple as possible. The deal covers both the Inventra soft cores and Mentor's physical libraries, including I/Os, memories and basic building blocks.

Per-usage payments
Jeff Lewis, marketing manager at Artisan Components, said Artisan's agreement with UMC, signed in September, covers both 0.25- and 0.18-micron libraries, following on a similar agreement with Taiwan Semiconductor Manufacturing Co. signed in August. Foundry customers essentially pay for the Artisan memory and I/O cores on a per-usage basis, based on how many chips are processed at the back end.

"The result is that pure-play foundries can extend their business, while Artisan still does the distribution and support for our cores," said Lewis. "The idea is that nobody gets paid until the customer is successful."

Alex Hinnawi, a UMC manager, said that in the 0.18-micron generation, where some 150 million transistors can be placed on a single die, foundries must take a more "comprehensive solution" view of their business, ranging from IP, embedded DRAM and flash, and test services. UMC has programs under way to move embedded-DRAM capabilities from today's 0.35-micron to UMC's 0.25-micron of ferings, though he declined to name the technology partners.

Also, UMC is working with NexFlash (Sunnyvale) to jointly develop an embedded-flash technology at the 0.25-micron generation. Discussions with NexFlash have not started on 0.18-micron flash development yet.

One problem ahead for UMC is mask costs. Hinnawi said a 0.18-micron mask set can cost half a million dollars or more, a situation that may inhibit smaller customers.

UMC is buying deep-ultraviolet (DUV) scanners at the 248-nm resolution to fabricate the 0.18-micron circuits, rather than the DUV steppers used for its 0.25-micron generation parts. For some back-end layers where the critical dimensions are less stringent, DUV steppers with optical-proximity correction can still be used. "With the scanners we can move forward to even smaller shrinks, into 0.15-micron and 0.12-micron processes," Cisneros said.

The Taiwan-based foundries have been competing fiercely to claim bragging rights as being ahead in 0.25-micron capacity. Both TSMC and UMC are investing billions.

UMC is building an enormous fab in the Hsinchu Science Industrial Park this year. Plans call for the nearly finished Fab 5 building to be equipped by mid-year, beginning a 0.18-micron ramp that will quickly shift to 0.15-micron design rules in 2000. That fab, when fully equipped, will be able to process 45,000 eight-inch wafers per month.

USIC, the UMC Group's newest fab, is now in initial operation. Another joint venture, USC, will reach 37,000 wafers per month when it hits peak capacity.

By the second quarter of 1999, the UMC Group expects to have 0.25-micron capacity of about 60,000 wafers per month.