iWave announces the Host controller for SDXC card which is compatible with the SD Physical Layer specification V3.0
- DS – Default speed mode upto 25MHz 3.3V signaling
- HS – High Speed mode upto 50MHz 3.3V signaling
- SDR12 – SDR upto 25MHz 1.8V signaling
- SDR25 – SDR upto 50MHz 1.8V signaling
- SDR50 – SDR upto 100MHz 1.8V signaling
- DDR50 – DDR upto 50MHz 1.8V signaling
The demo platform for the host controller is realized using Xilinx and Actel FPGA based platforms. The host interface in Actel is ARM based embedded CORTEX M soft core, in case of Xilinx it is microblaze based soft core.
Unlike the transition from SD to SDHC, which sometimes only required a firmware update, SDXC specification requires update in supporting peripheral system level set up also, e.g. for SDXC operation in SDR or DDR mode it is required that the SD signals from the Host controller change its operating voltage dynamically from 3.3V signaling to 1.8V. To achieve this in FPGA based platforms, extra I/Os and registers are included in the IP which will handle/control the external buffers that change the operating Voltage level as and when required.
The core developed supports following customizations
- FPGA: The design can be easily migrated to any specific FPGA technology as the modification/updation required is only in some FPGA specific macros like PLL/DCM and RAM instantiation
- Host interface: The standard core configuration has AHB LITE as the host interface. This can be easily migrated/changed according the required processor interface
- Applications: The end application of the SD Host controller may be vast. Hence the controller's features can be easily optimized to support the customers to fit in their specific design needs
iWave Systems Technologies is an embedded Hardware and Software Turnkey Design Services company, focused on providing integrated solutions for developing innovative products and systems in the areas of Communication, Consumer electronics and Multimedia.
|
iWave Systems Hot IP
Related News
- MIPI D-PHY v3.0 Doubles Data Rate of Physical Layer Interface While Extending Power Efficiency
- Arasan Announces Advanced Process Nodes for High Performance SD Card UHS-II Physical Layer Interface
- Arasan Chip Systems announces to offer SDIO/SD/MMC host controller compatible with BSquare’s Host Drivers on Win CE
- SD/eMMC Host and Device Controller IP Cores including matching PHYs with high performance, and high storage capacity available for license to secure your removable and embedded storage
- MIPI RFFE (RF Front-End Control Interface) v3.0 Master and Slave Controller IP Cores for ultimate control of your RF Front-end Cellular or Base station SoC's with Low Power Consumption and Reduced Latencies
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |