Dolphin Integration announces a benchmarking solution for fair comparison of the in-SoC performances of embedded memories
Basing the area assessment for memory instances on compiler outputs can only result in a biased density, as it does not take into account the in-SoC insertion overhead.
The unpleasant gap between the memory area generated by a compiler and the actual in-SoC area is comprised of several parts: abutment discrepancies, routing constraints, power supply mesh, possibly power rings, and flexibility of insertion with the appropriate number of metal layers, to name only the major ones.
LOGOS is an innovative “standard” enabling a fast and thorough comparison of the in-SoC area of memories. It involves 8 memory instances with a variable overall capacity to address various SoC Placement methods.
With LOGOS, the user can assess for instance the in-SoC memory area, the abutment and the routability on the top metal of the memory. Consequently, the LOGOS standard strengthens and speeds-up the identification process for the best library, while ensuring an accurate evaluation of silicon costs.
Memory users interested in the innovative LOGOS standard can gain access to Dolphin Integration website for this objective and fast benchmarking process of their current memory versus Dolphin Integration memory:
http://www.dolphin.fr/flip/ragtime/benchmark/ragtime_logos.php
About Dolphin Integration
Dolphin Integration is up to their charter as the most adaptive creator in Microelectronics to "enable mixed signal Systems-on-Chip", with a quality management stimulating reactivity for innovation. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components, resilient to noise and drastic for low power-consumption, together with engineering assistance and product evolutions customized to their needs.
For more information about Dolphin, visit: www.dolphin.fr/ragtime
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