Altera's RapidIO IP Core Passes RIOLAB Device Interoperability Testing
First FPGA Vendor to Offer RIOLAB-Qualified Serial RapidIO IP Core
San Jose, Calif., September 1, 2009—Altera Corporation (NASDAQ: ALTR) today announced its RapidIO® MegaCore function, version 9.0, successfully passed RIOLAB's Device Interoperability Level-3 (DIL-3) testing. Altera is the first FPGA vendor to offer a Serial RapidIO intellectual property (IP) core that is fully qualified by RIOLAB.
RIOLAB is the world's only independent RapidIO interoperability testing facility. DIL-3 is RIOLAB's final stage of device interoperability testing and ensures Altera's internally developed Serial RapidIO IP is interoperable with components, systems and software using RapidIO technology. The IP core works with Altera's Arria®, Cyclone® and Stratix® FPGAs and HardCopy® ASICs.
Altera's Serial RapidIO MegaCore function is designed to the RapidIO interconnect specification version 1.3. The core supports x1 and x4 lane widths at 1.25-Gbps, 2.5-Gbps and 3.125-Gbps lane rates, and allows for physical-, transport- and logical-layer separation. The endpoint IP core comes complete with test benches that provide proven interoperability with leading digital signal processor and switch vendors.
Altera offers a complete system-level, integration-ready Serial RapidIO solution that includes a Serial RapidIO IP core, reference designs and hardware development platforms. Designers can create custom systems to support their RapidIO architectures, including processor endpoints, digital signal processor endpoints with signal processing megafunctions, RapidIO switches, and a variety of RapidIO bridges that include PCI, PCI-X, HyperTransport™, system memory, and peripheral devices.
“Serial RapidIO is the interconnect technology of choice for many wireless, military and medical system designers who require a high level of security, data management and quality of service,” said Luanne Schirrmeister, senior director of component product marketing at Altera. “For these designers, passing RIOLAB's DIL testing gives them the added confidence that Altera's devices and RapidIO IP core are compatible and interoperable within their RapidIO system.”
Availability
The Serial RapidIO MegaCore function is available for download as part of the combined Quartus II Software/Altera MegaCore release at www.altera.com/pr090109/downloadcenter, and is supported within Altera's Quartus® II software version 9.0. The IP core is available as encrypted IP or as source code for complete user control.
About Altera
Altera® programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera's FPGA, CPLD and ASIC devices at www.altera.com.
|
Intel FPGA Hot IP
Related News
- Mobiveil's PCI Express 4.0 Endpoint Controller Passes PCI-SIG Gold and Interoperability Testing
- Mobiveil successfully completes RapidIO 3.1 IP (GRIO) interoperability testing with IDT's next generation RXS 50Gbps RapidIO switch
- Mobiveil's UNEX NVM Express IP Passes University of New Hampshire InterOperability Laboratory (UNH-IOL) Testing
- Altera's Stratix IV GT FPGA Successfully Passes Ethernet Alliance's HSE Interoperability Test Targeting 100-Gigabit Ethernet Systems
- ASIC Architect's PCI Express Switch Controller Core Passes PCI-SIG Compliance and Interoperability Testing
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |