English
Lattice Delivers Low Cost and Convenience to Designers of Consumer Products
Eight New Reference Designs and Two New Development Kits Target Low Power, Space Constrained Applications
HILLSBORO, OR -- Sep 08, 2009 -- Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of eight new reference designs, a $49 development kit for the ProcessorPM(TM) POWR605 power manager device and a $69 development kit for the ispMACH(R) 4000ZE CPLD, the ispMACH 4000ZE Pico Development Kit. The new kits are ideal for prototyping high volume, cost sensitive, low power, space constrained applications. System designers at OEMs and ODMs are increasingly using programmable logic devices in their systems as they face time-to-market pressures and design flexibility requirements that cannot be addressed by ASICs and ASSPs alone. Using Lattice's low-cost programmable logic solutions, designers can now introduce several versions of the same product with very short development cycles and make upgrades to existing products in the field with low risk.
The second-generation ispMACH 4000ZE CPLD family is ideal for ultra low-power, high-volume portable applications. The ispMACH 4000ZE family offers typical standby current as low as 10uA; ultra-small, space saving 0.4mm pitch Ball Grid Array packages; 3.3V, 2.5V and 1.8V I/O standards support; and 5-volt tolerant I/Os. Lattice's ispMACH 4000ZE CPLDs can be used for power management, level shifting and general purpose I/O expansion. The ProcessorPM (Processor Power Manager) POWR605 device monitors up to six circuit board power supplies and provides up to five open-drain digital I/Os. The device can generate signals such as a CPU Reset, including pulse stretching and power supply fault interrupt, using the on-chip 16 macrocell CPLD and four programmable timers. There are also two general purpose digital inputs, which can be used for other control functions such as manual reset input and watchdog timer input. The ProcessorPM device is available in a 4mm x 4mm, 24-pin QFNS package.
"Our new development kits highlight Lattice products that will dramatically cut cost and save power. Engineers who develop consumer products like handheld game consoles, digital set-top boxes and flat panel displays are under extreme pressure to deliver electronic systems rapidly with very low cost and power, and often in a tiny package. Lattice's new reference designs, which include I2C, SPI, LPC protocol bus controllers and processor support functions, are ideal for Lattice CPLD and power management devices and will ultimately save our customers design time," said Chris Fanning, Lattice Corporate Vice President and General Manger of Low Density and Mixed Signal Solutions.
The ispMACH 4000ZE Pico Development Kit
The ispMACH 4000ZE Pico Development Kit is an easy-to-use, low-cost platform for evaluating and designing with ispMACH 4000ZE CPLDs. The kit is based on a 2.5" x 2" evaluation board that features the ispMACH 4256ZE device in a lead-free 144-pin csBGA package, a Power Manager II POWR6AT6 for power monitoring, LCD panel and an expansion header. The Pico evaluation board provides features to help evaluate the use of the ispMACH 4000ZE CPLD in the context of battery-powered, handheld application. CPLDs are ideal for glue logic, level shifting between signal standards and providing additional interfaces for I/O limited microprocessors. On-board power monitoring circuits with the POWR6AT6 device provide a convenient way to monitor power consumption of the CPLD. A USB cable programming interface allows modification of the CPLD programming from any PC host. And by using ispLEVER(R) Classic and ispVM(TM) software, designers can compile their own designs captured as VHDL, Verilog HDL or schematics.
The kit includes demonstration designs pre-programmed into the ispMACH 4256ZE and POWR6AT6 devices that highlight key CPLD applications and power saving measures to maximize battery life. The CPLD demo design integrates an up/down counter, right/left shift register and an I2C bus master controller that communicates with the POWR6AT6. An LCD panel displays demo output using three characters.
Free ispLEVER Classic design software for the ispMACH 4000ZE can be downloaded from the Lattice website, www.latticesemi.com/products/designsoftware/isplever/ispleverclassic.
The ProcessorPM Development Kit
The ProcessorPM Development Kit is a versatile, ready-to-use hardware platform for evaluating and designing with ProcessorPM power management devices. The kit is based on a 2.5" x 2" evaluation board that features the ProcessorPM POWR605 device in a lead-free 24-pin QFN package, a Power Manager II POWR6AT6, evaluation circuits that emulate a power supply bus and processor interface, and an expansion header. The kit includes a preconfigured processor support demonstration design that will support hundreds of microprocessor, DSP, ASSP or ASIC power management scenarios. The demo integrates three key support functions for a processor: voltage supervisor, watchdog timer (WDT) and reset generator. The board is controlled with switches and push buttons. A slide potentiometer emulates brown-out conditions on a 2.5V supply rail. A pin header provides access to the voltage monitor inputs and digital IOs of the ProcessorPM device and the I2C and power supply margin/trim IOs of the POWR6AT6 device. Users may extend or modify the pre-configured demo using PAC-Designer(R) and ispVM software.
The kit includes a processor support demo that shows the versatility of the pre-configured ProcessorPM design by allowing modification of the WDT expiration period and reset pulse enable/disable with DIP switch settings. Users can then emulate supply rail conditions, manual reset inputs and the processor interface with push buttons and a slide potentiometer. The board indicates reset, interrupt and IO states with LEDs. If supply rails go out of tolerance, a manual reset occurs or, if the WDT period expires, the ProcessorPM device will assert processor control signals to indicate reset or WDT interrupt.
Free PAC-Designer design software for the Power Manager II family can be downloaded from the Lattice website, www.latticesemi.com/products/designsoftware/pacdesigner.
Pricing and Availability
Pricing for the ispMACH 4000ZE Pico Development Kit is $69 and the ProcessorPM Development Kit is $49. The kits are available for immediate ordering via the Lattice online store at www.latticesemi.com/store and through select authorized Lattice distributors at www.latticesemi.com/sales.
More information regarding the Pico Development Kit is available at www.latticesemi.com/4000ze-pico-kit and the ProcessorPM Kit at www.latticesemi.com/processorpm-kit. More information regarding the new reference designs is available at www.latticesemi.com/products/intellectualproperty/referencedesigns.
All ispMACH 4000ZE CPLDs and ProcessorPM devices are fully production qualified and available now for volume shipments.
About ispMACH 4000ZE CPLDs
The high performance ispMACH 4000ZE family offers an ultra low power CPLD solution. The ispMACH 4000ZE architecture features innovations that combine high performance with low power in a flexible CPLD family. For example, the family's Power Guard feature minimizes dynamic power consumption by preventing internal logic toggling due to unnecessary I/O pin activity. The ispMACH 4000ZE device combines high speed and low power with the flexibility needed for ease of design. With its robust Global Routing Pool and Output Routing Pool, the ispMACH 4000ZE family delivers excellent First-Time Fit, timing predictability, routing, pin-out retention and density migration. The ispMACH 4000ZE family offers densities ranging from 32 to 256 macrocells. There are multiple density-I/O combinations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA), and Ultra Chip Scale BGA (ucBGA) packages ranging from 32 to 144 pins/balls. A user programmable internal oscillator and a timer are included in the device for tasks like LED control, keyboard scanner and similar housekeeping type state machines. This feature can be optionally disabled to save power. For more information about the Lattice ispMACH 4000ZE CPLD family, visit www.latticesemi.com/products/cpldspld/ispmach4000ze.cfm
About ProcessorPM Power Management Devices
Lattice's Power Manager II ProcessorPM POWR605 device is a general purpose power-supply monitor, reset generator and watchdog timer, incorporating both in-system programmable logic and analog functions implemented in non-volatile E2CMOS(R) technology. The ProcessorPM POWR605 device provides six independent analog input channels to monitor power supply voltages. Two general purpose digital inputs are also provided for miscellaneous control functions. The ProcessorPM POWR605 device provides up to five open drain digital outputs that can be used for controlling DC-DC converters, low-drop-out regulators (LDOs) and optocouplers, as well as supervisory and general purpose logic interface functions. The five digital, open drain outputs can be optionally configured as digital inputs to sense more input signals as needed, such as manual reset. For more information about the Lattice Power Manager II device family, visit www.latticesemi.com/products/powermanager.
About Lattice Semiconductor
Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. For more information, visit www.latticesemi.com
HILLSBORO, OR -- Sep 08, 2009 -- Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of eight new reference designs, a $49 development kit for the ProcessorPM(TM) POWR605 power manager device and a $69 development kit for the ispMACH(R) 4000ZE CPLD, the ispMACH 4000ZE Pico Development Kit. The new kits are ideal for prototyping high volume, cost sensitive, low power, space constrained applications. System designers at OEMs and ODMs are increasingly using programmable logic devices in their systems as they face time-to-market pressures and design flexibility requirements that cannot be addressed by ASICs and ASSPs alone. Using Lattice's low-cost programmable logic solutions, designers can now introduce several versions of the same product with very short development cycles and make upgrades to existing products in the field with low risk.
The second-generation ispMACH 4000ZE CPLD family is ideal for ultra low-power, high-volume portable applications. The ispMACH 4000ZE family offers typical standby current as low as 10uA; ultra-small, space saving 0.4mm pitch Ball Grid Array packages; 3.3V, 2.5V and 1.8V I/O standards support; and 5-volt tolerant I/Os. Lattice's ispMACH 4000ZE CPLDs can be used for power management, level shifting and general purpose I/O expansion. The ProcessorPM (Processor Power Manager) POWR605 device monitors up to six circuit board power supplies and provides up to five open-drain digital I/Os. The device can generate signals such as a CPU Reset, including pulse stretching and power supply fault interrupt, using the on-chip 16 macrocell CPLD and four programmable timers. There are also two general purpose digital inputs, which can be used for other control functions such as manual reset input and watchdog timer input. The ProcessorPM device is available in a 4mm x 4mm, 24-pin QFNS package.
"Our new development kits highlight Lattice products that will dramatically cut cost and save power. Engineers who develop consumer products like handheld game consoles, digital set-top boxes and flat panel displays are under extreme pressure to deliver electronic systems rapidly with very low cost and power, and often in a tiny package. Lattice's new reference designs, which include I2C, SPI, LPC protocol bus controllers and processor support functions, are ideal for Lattice CPLD and power management devices and will ultimately save our customers design time," said Chris Fanning, Lattice Corporate Vice President and General Manger of Low Density and Mixed Signal Solutions.
The ispMACH 4000ZE Pico Development Kit
The ispMACH 4000ZE Pico Development Kit is an easy-to-use, low-cost platform for evaluating and designing with ispMACH 4000ZE CPLDs. The kit is based on a 2.5" x 2" evaluation board that features the ispMACH 4256ZE device in a lead-free 144-pin csBGA package, a Power Manager II POWR6AT6 for power monitoring, LCD panel and an expansion header. The Pico evaluation board provides features to help evaluate the use of the ispMACH 4000ZE CPLD in the context of battery-powered, handheld application. CPLDs are ideal for glue logic, level shifting between signal standards and providing additional interfaces for I/O limited microprocessors. On-board power monitoring circuits with the POWR6AT6 device provide a convenient way to monitor power consumption of the CPLD. A USB cable programming interface allows modification of the CPLD programming from any PC host. And by using ispLEVER(R) Classic and ispVM(TM) software, designers can compile their own designs captured as VHDL, Verilog HDL or schematics.
The kit includes demonstration designs pre-programmed into the ispMACH 4256ZE and POWR6AT6 devices that highlight key CPLD applications and power saving measures to maximize battery life. The CPLD demo design integrates an up/down counter, right/left shift register and an I2C bus master controller that communicates with the POWR6AT6. An LCD panel displays demo output using three characters.
Free ispLEVER Classic design software for the ispMACH 4000ZE can be downloaded from the Lattice website, www.latticesemi.com/products/designsoftware/isplever/ispleverclassic.
The ProcessorPM Development Kit
The ProcessorPM Development Kit is a versatile, ready-to-use hardware platform for evaluating and designing with ProcessorPM power management devices. The kit is based on a 2.5" x 2" evaluation board that features the ProcessorPM POWR605 device in a lead-free 24-pin QFN package, a Power Manager II POWR6AT6, evaluation circuits that emulate a power supply bus and processor interface, and an expansion header. The kit includes a preconfigured processor support demonstration design that will support hundreds of microprocessor, DSP, ASSP or ASIC power management scenarios. The demo integrates three key support functions for a processor: voltage supervisor, watchdog timer (WDT) and reset generator. The board is controlled with switches and push buttons. A slide potentiometer emulates brown-out conditions on a 2.5V supply rail. A pin header provides access to the voltage monitor inputs and digital IOs of the ProcessorPM device and the I2C and power supply margin/trim IOs of the POWR6AT6 device. Users may extend or modify the pre-configured demo using PAC-Designer(R) and ispVM software.
The kit includes a processor support demo that shows the versatility of the pre-configured ProcessorPM design by allowing modification of the WDT expiration period and reset pulse enable/disable with DIP switch settings. Users can then emulate supply rail conditions, manual reset inputs and the processor interface with push buttons and a slide potentiometer. The board indicates reset, interrupt and IO states with LEDs. If supply rails go out of tolerance, a manual reset occurs or, if the WDT period expires, the ProcessorPM device will assert processor control signals to indicate reset or WDT interrupt.
Free PAC-Designer design software for the Power Manager II family can be downloaded from the Lattice website, www.latticesemi.com/products/designsoftware/pacdesigner.
Pricing and Availability
Pricing for the ispMACH 4000ZE Pico Development Kit is $69 and the ProcessorPM Development Kit is $49. The kits are available for immediate ordering via the Lattice online store at www.latticesemi.com/store and through select authorized Lattice distributors at www.latticesemi.com/sales.
More information regarding the Pico Development Kit is available at www.latticesemi.com/4000ze-pico-kit and the ProcessorPM Kit at www.latticesemi.com/processorpm-kit. More information regarding the new reference designs is available at www.latticesemi.com/products/intellectualproperty/referencedesigns.
All ispMACH 4000ZE CPLDs and ProcessorPM devices are fully production qualified and available now for volume shipments.
About ispMACH 4000ZE CPLDs
The high performance ispMACH 4000ZE family offers an ultra low power CPLD solution. The ispMACH 4000ZE architecture features innovations that combine high performance with low power in a flexible CPLD family. For example, the family's Power Guard feature minimizes dynamic power consumption by preventing internal logic toggling due to unnecessary I/O pin activity. The ispMACH 4000ZE device combines high speed and low power with the flexibility needed for ease of design. With its robust Global Routing Pool and Output Routing Pool, the ispMACH 4000ZE family delivers excellent First-Time Fit, timing predictability, routing, pin-out retention and density migration. The ispMACH 4000ZE family offers densities ranging from 32 to 256 macrocells. There are multiple density-I/O combinations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA), and Ultra Chip Scale BGA (ucBGA) packages ranging from 32 to 144 pins/balls. A user programmable internal oscillator and a timer are included in the device for tasks like LED control, keyboard scanner and similar housekeeping type state machines. This feature can be optionally disabled to save power. For more information about the Lattice ispMACH 4000ZE CPLD family, visit www.latticesemi.com/products/cpldspld/ispmach4000ze.cfm
About ProcessorPM Power Management Devices
Lattice's Power Manager II ProcessorPM POWR605 device is a general purpose power-supply monitor, reset generator and watchdog timer, incorporating both in-system programmable logic and analog functions implemented in non-volatile E2CMOS(R) technology. The ProcessorPM POWR605 device provides six independent analog input channels to monitor power supply voltages. Two general purpose digital inputs are also provided for miscellaneous control functions. The ProcessorPM POWR605 device provides up to five open drain digital outputs that can be used for controlling DC-DC converters, low-drop-out regulators (LDOs) and optocouplers, as well as supervisory and general purpose logic interface functions. The five digital, open drain outputs can be optionally configured as digital inputs to sense more input signals as needed, such as manual reset. For more information about the Lattice Power Manager II device family, visit www.latticesemi.com/products/powermanager.
About Lattice Semiconductor
Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. For more information, visit www.latticesemi.com
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