Deal gives ARC its own Java accelerator
![]() |
Deal gives ARC its own Java accelerator
By Chris Edwards, EE Times UK
February 18, 2002 (12:44 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020218S0014
UK intellectual property (IP) supplier DCT has found a way to speed up Java processing on ARC International's processor core without adding any specific Java instructions to the architecture. The companies have cut a deal that will see ARC market DCT's Java accelerator as part of the ARCtangent-A4 core, with the two partners splitting royalties. The software for the DCT-ARC Java processor is based on open-source Kaffe software. The core has about 5000 extra logic gates. DCT's work takes advantage of the way that the ARCtangent handles registers to speed up Java virtual machine instructions without creating new instructions. Matt Kubiczek, chief technology officer and founder of DCT, said: "It is a combinatorial bit of hardware between the instruction fetch and operand fetch parts of the pipeline. There is no extra pipeline stage. Other techniques, such as [ARM Holdings'] Jazelle, add a pipeline stage." With the DCT hardware , the ARC core does not run Java byte codes directly. Instead, the hardware is tuned to speed up operations that manipulate data sitting on a stack. The JVM is based on a stack architecture, but most risc processors use a bank of directly addressable registers, not a stack. The DCT hardware allocates an extra set of registers in the ARC processor that are addressed as a stack. Any instructions that access those registers are assumed to work in stack mode, in contrast to their behaviour when used on the main register file. Because the processor does not execute Java byte codes directly, they have to be converted to modified behaviour ARC instructions. "The translation is performed by the class loader into simple augmented ARC instructions or into threaded calls or subroutines," said Kubiczek. The more complex byte codes, such as those that load an object, are translated into subroutines. More simple arithmetic byte codes can be converted in one ARC instruction or reduced to one part of an instruction. The translation can either happen at runtime, for downloaded classes, or the pre-translated code can be stored in rom and run directly. "There is no dynamic translation as in the Nazomi approach. The overhead is the look-up needed to translate the JVM byte codes [when the class is loaded]," said Kubiczek. As the register file is limited in size, the DCT accelerator deals with deep stack operations by flushing out data to main memory and then reloading when it is needed. The procedure is similar to that performed by the Sun Sparc processor, which makes extensive use of register 'windowing'. But the DCT engine dynamically remaps registers so that the top of the stack can move to any point within the register file. "The good thing about Java is that every method declares its maximum stack usage. The manipulation can be done by method prologue and epilogue code," said Kubiczek. The software for the DCT-ARC Java processor is based on the open-source Kaffe software. ARC will sell the Java core, which has about 5000 extra logic gates, and split the royalties between itself and DCT.
Related News
- Acquisition of Cognovo gives u-blox own 4G chip technology
- ARC International and Tao Group Provide the Lowest Power Java Solution for Embedded Devices
- inSilicon JVX[tm] Accelerator Speeds Java Technology-based Wireless Internet Products
- JEDI Technologies Delivers Java Acceleration Solution for MIPS-Based Processors JSTAR Accelerator is Particularly Appealing for Wireless Internet Applications
- Startups, Nazomi Communications Inc. and Chicory Systems Inc., aim new Java chips at accelerator role
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |