Long, bumpy transition seen for USB 3.0
OEMs fear delays in Intel, Microsoft support
Rick Merritt, EETimes
(09/21/2009 6:00 AM EDT)
SAN JOSE, Calif. — The Intel Developer Forum is expected to generate buzz around SuperSpeed USB this week, but the transition to the 5 GHz interface may be slower and bumpier than many would hope due to cost, power and support issues.
At least two sources said Intel Corp. may not hit its schedule for sampling PC chip sets supporting USB 3.0 in the first quarter 2010, a key trigger for a volume market ramp. One source said the chip sets could be delayed as much as a year.
Intel declined to comment on its USB 3.0 plans prior to this week's IDF. Typically, Intel triggers the volume ramp of new interfaces such as USB 3.0 by supporting the technology in its PC chip sets, enabling a generation of desktops and notebooks and creating an opportunity for supporting peripherals.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Search Verification IP
Related News
- Orange Tree announces SuperSpeed USB 3.0 FPGA module
- Innovative Logic Inc. and M31 Technology Introduce a USB-IF Certified Complete SuperSpeed USB 3.0/2.0 Dual Role IP Solution
- Innovative Logic Inc. and M31 Technology Introduce a USB-IF Certified Complete SuperSpeed USB 3.0 IP Solution
- USB-IF Certifies 1,000 SuperSpeed USB (USB 3.0) Products
- Innovative Logic announced licensing of their USB 3.0 SuperSpeed OTG IP
Breaking News
- Ceva Neural Processing Unit IP for Edge AI Selected by Nextchip for Next-Generation ADAS Solutions
- Cadence Advances AI in the Cloud with Industry-First DDR5 12.8Gbps MRDIMM Gen2 Memory IP System Solution
- Thalia joins GlobalFoundries' GlobalSolutions Ecosystem to advance IP reuse and design migration
- MosChip® to showcase Silicon Engineering Services at TSMC 2025 North America Technology Symposium
- Alphawave Semi Audited Results for the Year Ended 31 December 2024
Most Popular
- New Breakthroughs in China's RISC-V Chip Industry
- Cadence to Acquire Arm Artisan Foundation IP Business
- Analog Bits to Demonstrate IP Portfolio on TSMC 3nm and 2nm Processes at TSMC 2025 Technology Symposium
- JEDEC® and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard: Advancing Bandwidth, Efficiency, and Capacity for AI and HPC
- Shifting Sands in Silicon by Global Supply Chains