English
Moortec Announces SPI Block (MR74040) for Low Power Applications
September 29, 2009 -- Moortec Announces SPI Block (MR74040) for Low Power Applications. The MR74040 is a synchronous serial-data interface adhering to the SPI protocol of communications. Configurable for all 4 SPI modes* this block acts as a single slave. The design targets the 0.18um CMOS (ca18ha) process offered by Jazz. The MR74040 consists of 32, 16-bit wide R/W registers, 28 of which can be configured in to a ‘power down’ state for low power operation when idle.
About Moortec
Moortec, established in 2005, provide high quality analogue and mixed-signal IP blocks as well as Custom Chip solutions world-wide for a variety of applications. The UK based design group also provide Platforms for IC test and evaluation. Having a track record of delivery to tier-1 semiconductor and product companies, Moortec provide a quick and efficient path to market for customer products.
* Silicon proven for mode 3 only
|
||||||
Related News
- Digital Blocks I2C & SPI Controller IP Core Families Extend Leadership in Sensor Interface to Host Processors with System-Level Features & Low Power
- Digital Blocks I2C & SPI Controller IP Core Families Extend Lead in Sensor Interface to Host Processors with System-Level Features & Low Power
- Advanced USB 3.0 IP in 22nm boasting a very low power ULP and ULL Technology Licensed to Over 10 Global Customers
- Ceva Bluetooth Low Energy and 802.15.4 IPs Bring Ultra-Low Power Wireless Connectivity to Alif Semiconductor's Balletto Family of MCUs
- Efinix Releases Topaz Line of FPGAs, Delivering High Performance and Low Power to Mass Market Applications
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |