Magma RTL-to-GDSII Implementation Selected by Mellanox Technologies for 40-nm Multimillion-gate Communications ICs
Talus 1.1 Proven to Deliver Optimum Power and Performance
SAN JOSE, Calif., Oct. 26, 2009 -- Magma(R) Design Automation Inc. (Nasdaq:LAVA), a provider of chip design software, today announced that Mellanox Technologies, a leading supplier of end-to-end connectivity solutions for servers and storage that optimize data center performance, has selected the Talus(R) 1.1 RTL-to-GDSII implementation system to be included in its 40-nanometer (nm) IC design flow. A long-time user of Magma software, Mellanox Technologies upgraded to the latest version of Talus after an extensive evaluation proved its ability to deliver optimum power and performance on multimillion-gate designs.
"Mellanox Technologies' chips are complex and typically contain 10 million gates or more," said Premal Buch, general manager of Magma's Design Implementation Business Unit. "When the company migrated to 40-nm processes, minimizing area and reducing power and tape-out time continued to be key goals. With the new Talus Flow Manager, COre(TM) (Concurrent optimizing routing engine) technology, high capacity and proven performance across 50 40-nm designs, Talus 1.1 is the best solution for these advanced ICs."
"Over the past 4 years we have taped out multiple complex chips that support high-speed InfiniBand and Ethernet interconnects using Magma's software," said Shai Cohen, vice president of operations and engineering at Mellanox Technologies.
Talus 1.1: Fastest Path to Silicon for 45-/40-nm Chips
The Talus system was built to anticipate the unique requirements of chip design at advanced process nodes, and Talus 1.1 takes its capabilities even further. Since its availability was announced in May 2009, Magma customers have found Talus 1.1 to deliver significant improvements in runtime and timing convergence. It also achieves timing closure with no design-rule checking (DRC) violations and reduces total chip area significantly. Talus also offers a significant capacity advantage over competing systems which allows design teams to work on much larger blocks during the design process.
Talus Flow Manager: Improved Ease of Use with Out-of-the-Box Flows
Talus 1.1 introduces the new Talus Flow Manager that provides an out-of-the-box RTL-to-GDSII design flow tuned to deliver optimal results. Designers can easily customize the reference flow and tailor it to their own needs, developing specific flows for various projects or applications. Additional reference flows include templates for the implementation of multiple-voltage (MVdd), multiple-mode and multiple-corner (MMMC) designs, as well as low-power and high-performance designs. Ease of use and cost of adoption is dramatically improved through the use of these pre-qualified flows.
About Magma
Magma's electronic design automation (EDA) software provides the "Fastest Path to Silicon"(TM) and enables the world's top chip companies to create high-performance integrated circuits (ICs) for cellular telephones, electronic games, WiFi, MP3 players, digital video, networking and other electronic applications. Magma products are used in IC implementation, analog/mixed-signal design, analysis, physical verification, circuit simulation and characterization. The company maintains headquarters in San Jose, Calif., and offices throughout North America, Europe, Japan, Asia and India. Magma's stock trades on NASDAQ under the ticker symbol LAVA. Follow Magma on Twitter at www.Twitter.com/MagmaEDA and on Facebook at www.Facebook.com/Magma. Visit Magma Design Automation on the Web at www.magma-da.com.
|
Related News
- eInfochips Strengthens RTL-to-GDSII Design Service Capabilities, Adopts Magma IC Implementation Flow
- Magma and ARM Release Reference Methodology for RTL-to-GDSII Implementation of ARM9E(TM) Family
- Freescale Semiconductor Uses Cadence Encounter RTL-to-GDSII Flow to Tapeout a 28nm 1.8GHz Communications Processor
- Adapteva Uses Magma's RTL-to-GDSII Flow to Tape Out a 28-nm 64-Core Microprocessor Chip
- Magma's Titan Mixed-Signal Platform Supports TSMC's 65- and 40-nm Interoperable Process Design Kits (iPDKs)
Breaking News
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |