New Tensilica DPU Family Delivers 10 GigaMAC/sec DSP Performance, Tops 1 GHz Mark
Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)
Xtensa LX3 Customizable Dataplane Cores Tailored for High Performance DSP
SANTA CLARA, Calif. - November 2, 2009 - Tensilica, Inc. today introduced the Xtensa LX3 high-performance dataplane processor (DPU) core optimized for digital signal processing (DSP) and control in the system-on-chip (SOC) dataplane. The Xtensa LX3 DPU offers the industry's widest range of pre-verified DSP options ranging from a simple floating point accelerator to a 16-MAC (multiply accumulator) vector DSP powerhouse.
The base Xtensa LX3 DPU configuration can reach speeds of over 1 GHz in 45nm process technology (45GS) with an area of just 0.037 mm2 and power of 0.015 mW/MHz. When built with the new ConnX Baseband Engine DSP (ConnX BBE), the Xtensa LX3 processor delivers over 10 Giga-MACs-per-second performance, running at 625 MHz with a footprint of 0.93mm2 (post place-and-route 45GS) and consuming just 170 mW (including leakage).
The Xtensa LX3 DPU has been fine-tuned with optimized scripts for the latest generation of EDA tools, to deliver even better speed-power-area results than the predecessor Xtensa LX2 cores. When comparing functionally equivalent configurations of the Xtensa LX3 DPU versus the prior generation Xtensa LX2 DPU, the new Xtensa LX3 processor delivers up to 15 percent faster clock speed, up to 20 percent smaller die area and up to 15 percent less power using identical process technologies and libraries.
"The Xtensa LX3 processor, Tensilica's flagship product, provides significant speed and power improvements to enable efficient digital signal processing and control processing in SOC or mixed signal devices," stated Jack Guedj, Tensilica's president and CEO. "We've invested heavily in our DPU technology to make it smaller, easier to use, and up to 20 percent faster, providing designers with the performance levels and connectivity expected from custom RTL blocks along with the programmability and debug benefits of conventional processors. And since Xtensa LX3 cores are pre-verified modules, it significantly reduces design risks for dataplane design compared to traditional custom hardware RTL design approaches."
Broadest Choice of DSP Options
The Xtensa LX3 DPU offers a wide array of pre-verified DSP options. Of course, designers can create their own DSP functionality using Tensilica's highly automated extensibility, but these pre-verified options speed up SOC time to market. The options include:
- ConnX D2 DSP - a new 16-bit dual-MAC SIMD (single instruction multiple data) DSP for communications, announced August 24, 2009
- ConnX Vectra LX DSP - an updated 16-bit quad-MAC SIMD DSP for communications (with new option for single load/store unit)
- HiFi 2 audio DSP - the most widely licensed audio DSP on the market today, a 24-bit, dual-MAC audio processor
- A 32-bit IEEE-754 compliant single-precision floating point unit
- A new 64-bit IEEE-754 compliant double precision floating point accelerator.
Easy System Integration
The Xtensa LX3 DPU was designed with multi-function, multi-core SOC designs in mind. Designers can easily connect the Xtensa LX3 DPU to the other elements of their SOC design in a variety of both traditional processor-centric and RTL-centric styles.
Using a standard 32-bit, 64-bit or 128-bit system bus, Tensilica offers support for AMBA AHB-Lite and AXI bridges with asynchronous or synchronous clocks.
However, designers also can bypass the system bus altogether in order to achieve much higher input/output throughput and seamless integration with RTL via customizable Ports and Queues. These Ports and Queues let designers connect directly to RTL, allowing huge amounts of data to be transferred on each cycle without the need for separate load/store operations on the processor. For memory lookups, designers can connect lookup and scratchpad RAMs, as well as other long-latency hardware computation units, directly to the Xtensa DPU.
Performance Leadership Extended
Tensilica's Xtensa DPUs are the lowest power, highest performance licensable cores on the market based on previous industry standard benchmarks (see http://www.tensilica.com/products/xtensa-customizable/xtensa-lx2/benchmarks.htm ) that are still not equaled by the competition.
Availability
The Xtensa LX3 customizable DPU is available now.
About Tensilica
Tensilica, Inc. - the leader in customizable dataplane processors - is a semiconductor IP licensor recognized by the Gartner Group as the fastest growing semiconductor IP supplier in 2008. Dataplane Processor Units (DPUs) combine the best capabilities of CPUs and DSPs while delivering 10-to-100-times the performance because they can be customized using Tensilica's automated design tools to meet specific dataplane performance targets. Tensilica's DPUs power SOC designs at system OEMs and five out of the top 10 semiconductor companies for products including mobile phones, consumer electronics devices (including digital TV, Blu-ray Disc players, broadband set top boxes and portable media players), computers, and storage, networking and communications equipment. For more information on Tensilica's patented, benchmark-proven DPUs visit www.tensilica.com.
|
Related News
- New Cadence Tensilica FloatingPoint DSP Family Delivers Scalable Performance for a Broad Range of Compute-Intensive Applications
- Synopsys' New Embedded Vision Processor IP Delivers Industry-Leading 35 TOPS Performance for Artificial Intelligence SoCs
- Flex Logix Launches NMAX Neural Inferencing Engine that Delivers 1 to 100+ TOPS Performance Using 1/10th the Typical DRAM Bandwidth
- Phison Licenses Tensilica's Dataplane Processor (DPU) for NAND Flash Memory Controllers and SSD Applications
- Tilera's TILE-Gx Processor Family Expands With a 9-Core Offering, Providing Unparalleled Integration and Performance at Under 10 Watts
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models
Most Popular
E-mail This Article | Printer-Friendly Page |