Tiempo demonstrates breakthrough performance for contactless secured applications, improving processing speed by a factor 6
Grenoble, France – November 16, 2009 – Tiempo is demonstrating at the “Cartes 2009” event how its asynchronous design technology can dramatically improve processing speed for contactless applications with, as an illustration, a live demo of a secured PayPass™ transaction in which processing speed on the card is six times faster than industry implementations, showing a complete transaction in less than 60 ms.
“Tiempo asynchronous – or clockless –technology allows designing ICs which are ultra-low power and high performance” says Marc Renaudin, CTO at Tiempo. “For contactless applications, we typically deliver 6 times more processing power than industry state-of-the-art clocked circuits. Additionally, our delay insensitive technology allows us to take full advantage of the remote power source by automatically adapting the circuit speed to the available energy.”
Using Tiempo innovative design flow, such highly performing hardware can be described with a standard hardware description language, synthesized with ACC, Tiempo unique asynchronous circuit compiler, then verified and placed-and-routed with standard simulation and back-end tools.
“Asynchronous design is the next breakthrough for the ever growing contactless applications” says Serge Maginot, CEO of Tiempo. “We are filling the gap between high processing applications such as banking or ePassport and fast applications such as ticketing. We offer a technology which can deliver performances never seen on traditional clocked circuits for smart cards, while increasing the security level”.
Furthermore, Tiempo asynchronous technology significantly increases the level of security of circuits, as concluded by Brightsight, a well-established and independent lab. The result of a preliminary study states that “Tiempo asynchronous technology is very likely to increase resistance against power analysis and perturbation attacks”.
A live PayPass™ demonstration as well as performance outlook for other applications is demonstrated on Tiempo booth (#3D095) at Cartes 2009, November 17-19, 2009, Paris, France.
About Tiempo
Tiempo develops and commercializes Core IPs for the design of innovative integrated circuits that are ultra-low power, ultra-low noise, ultra-low voltage, robust versus PVT variations and highly secured. Tiempo IP portfolio includes ultra-low power and secured asynchronous cores of microcontrollers, microprocessors and crypto-processors, and is supported by an automated synthesis tool using standard input language. Targeted core applications are chips for low-power embedded electronics and secured devices.
|
Related News
- Tiempo, IP company with breakthrough ultra-low power asynchronous design technology, raises 5 million Euros ($7 million) in Series B funding
- Tiempo Demonstrates the First Asynchronous Synthesis Tool Using Standard Languages
- INSIDE Contactless and TIEMPO Announce Partnership on Next Generation Chip Product
- Xilinx Delivers Breakthrough Design Tool For High Performance Signal Processing With New System Generator For DSP v6.3I
- Flow Computing Emerges from Stealth with Licensable, On-Die Parallel Processing Enabling 100X Improved Performance For Any CPU Architecture
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |