Atrenta's SpyGlass-CDC Solution Boosts IP Integration Efficiency for Fujitsu Kyushu Network Technologies
San Jose, Calif., Nov. 17, 2009 - Atrenta Inc., the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow, today announced that Fujitsu Kyushu Network Technologies, a leader in innovative technologies for network and service management solutions, has adopted its SpyGlass®-CDC product. Fujitsu Kyushu Network Technologies will broadly deploy the tool to help reduce design risks associated with semiconductor IP integration.
Early Design Closure solutions from Atrenta allow design capture, verification, optimization and exploration early in the design flow at the register transfer language (RTL) stage, when it's faster and easier to correct problems and explore alternatives. This approach facilitates propagation of design efficiencies to detailed, back-end implementation with minimized schedule risk.
Atrenta's SpyGlass-CDC product analyzes system-on-chip (SoC) designs to ensure complex clock synchronization schemes such as FIFOs and handshakes are correct. Bugs in faulty clock domain synchronizations between IP blocks on a chip are hard to find with conventional design tools and represent a leading cause of chip re-spins and field reliability issues. "Atrenta's SpyGlass-CDC product allows us to ensure correct clock synchronization in our complex ASIC and FPGA designs," said Yuji Yoshitani, senior engineer at Fujitsu Kyushu Network Technologies System Logic Development Center. "We have deployed SpyGlass-CDC as a mandatory part of our ASIC and FPGA design flows to verify correct synchronization as early as possible and allow us to take corrective action if necessary."
"The use of third party semiconductor IP from multiple sources, with multiple clock domains, is a fact of life these days for complex SoCs," said Mike Gianfagna, vice president of marketing at Atrenta. "Our SpyGlass-CDC product is very effective at finding clock synchronization bugs that can easily become chip killers. We're delighted that Fujitsu Kyushu Network Technologies has chosen SpyGlass to assist with their leading edge designs."
About Atrenta
Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 150 customers, including the world's top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure. For more information, visit www.atrenta.com.
|
Related News
- Fujitsu Kyushu Network Technologies Limited Adopts Atrenta's SpyGlass AutoVerify for RTL Functional Checks
- Boosting Efficiency and Reducing Costs: Silvaco's Approach to Semiconductor Fabrication
- NEDO Approves Rapidus' FY2024 Plan and Budget for "Research and Development of 2nm-generation semiconductor integration technology and short TAT manufacturing technology based on Japan-US collaboration"
- InterMotion Technology boosts IP verification productivity for Lattice Semiconductor's CrossLink FPGA family using Aldec's Active-HDL
- Fujitsu Semiconductor and Mie Fujitsu Semiconductor License Nantero's NRAM And Have Begun Developing Breakthrough Memory Products for Multiple Markets
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |