7 µW always on Audio feature extraction with filter banks on TSMC 22nm uLL
Dolphin Integration promotes a design methodology ensuring High-Yield circuits despite Mismatch
Meylan, France – December 4th, 2009. As the promoter of innovative Virtual Components of Silicon IP and methodologies for the Microelectronics Design Industry, Dolphin Integration takes the responsibility of setting up a method enabling the assessment of design yield for any memory generator.
Traditional simulations based on worst-case corners (process, temperature, voltage) do not allow measuring the negative impact of the performance variations of transistors due to the dispersion between transistors on the same circuit.
To take into consideration such Mismatch effects, Monte Carlo simulations are required, resulting in a huge amount of computer time. For a memory generator, simplifications of models are necessary, but must result in a safe design. In any case, what is missing is a standard method for assessing the design yield of a memory during simulation and specifications based on clear acceptance criteria.
Design yield can only be guaranteed by a combination of worst-case corners simulation and mismatch simulation. The embedded Memory Provider has built a two steps methodology to take into account the offset for the design and the validation of any memory generator, with the objective of achieving high design yield while maintaining optimized performances. The Dolphin method enables both an a-posteriori verification of mismatch and an a-priori implementation during the memory design.
SoC designers can benefit from both Dolphin Integration’s design methodology and an overall catalog of Static RAM and Via-Programmable ROM satisfying the expectations of most of consumer and industrial applications.
For more information about Dolphin Integration’s offering: http://www.dolphin.fr/flip/ragtime/ragtime_download.html
About Dolphin Integration
Dolphin Integration is up to their charter as the most adaptive creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation and Foundry independence. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components, resilient to noise and drastic for low power-consumption, together with engineering assistance and product evolutions customized to their needs.
For more information about Dolphin, visit www.dolphin.fr/ragtime
|
Dolphin Design Hot IP
Related News
- Dolphin Integration helps reducing BoM cost of IoT circuits thanks to a Panoply of Over Voltage regulators
- Dolphin Integration announces a million of circuits sold over the last two years
- DOLPHIN Integration is completing its offering of Custom Training Products after a market test in Asia
- DOLPHIN Integration promotes a complete offering of detectors for on-the-fly checking
- DOLPHIN Integration promotes equivalence checking for multi-level modeling
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |