English
STMicroelectronics selects Cadence's Virtual Component Co-Design (VCC)
 |
STMicroelectronics selects Cadence
By David Larner, Embedded Systems
November 19, 2001 (4:50 a.m. EST)
URL: http://www.eetimes.com/story/OEG20011119S0002
STMicroelectronics has announced that it has selected Cadence's Virtual Component Co-Design (VCC) for both its Automotive and Digital Consumer platform system-level design methodology and design flow. STMicroelectronics' Audio & Automotive Division uses VCC for behavioural modelling and architectural exploration in automotive design flows. For ST's new power train architecture project, VCC addresses those system-level parts of the design flow that significantly influence SoC size and complexity. This includes behavioural modelling and architecture exploration to enable knowledge transfer with internal and external system customers, and design refinement and export to implementation-level co-verification. STMicroelectronics, one of the world's largest semiconductor manufacturers and a leading supplier of system-on-chip (SoC) solutions, was one of the original VCC development partners.
Related News
- Cadence halts sales of Cierto VCC co-design tool
- Cadence and Spreadtrum Collaborate on Virtual Reference Design Kit to Reduce Customers' Design Cycle by Up to 12 Weeks
- New Integration Between SpaceStudio Hardware Software Co-design and European Space Agency’s TASTE Tool Set
- Toshiba announces co-design/co-verification platform for collaborative development of chip, package and PCB system
- Cochlear Limited Selects AMI Semiconductor to Co-Design and Manufacture Future Generation DSP Based System-on-Chip for Cochlear Implants
Breaking News
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |