Anne-Francoise Pele, EE Times
(12/09/2009 6:33 AM EST)
PARIS — A fundamental problem in the industry is to analyze and implement the tradeoffs between improving IP quality and losing design productivity. During a panel discussion at the IP-ESC 2009 Conference last week in Grenoble, France, IP buyers and sellers confronted experiences and issues.
Franois Rémond, director, CAD & design methodology at STMicroelectronics NV (Geneva, Switzerland), recognized that, over the last few years, SoC design productivity raised thanks to IP-based integration methods. At the same time, he observed that IP quality improved with costly investments in design for reuse methods.
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