Renesas Adopts Cadence Virtuoso Technology for Mixed-Signal and Analog Design at its Global Design Centers
Constraint-Driven Design and Verification Expected to Reduce Turnaround Time by 30%
SAN JOSE, Calif. -- Jan 26, 2010 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced that Renesas Technology Corp. has upgraded to the latest version of Cadence® Virtuoso® technology at its global design centers. Renesas anticipates the constraint-driven design and verification capabilities in Virtuoso IC 6.1 will shave up to 30 percent off the turnaround time for its mixed-signal and analog designs while maintaining their high quality standards.
“Through our extensive evaluation, we now have confidence that Virtuoso IC 6.1 significantly shortens design turnaround time and brings us unparalleled productivity gains in our analog/mixed-signal designs,” said Takao Sato, department manager, SIP & Analog EDA Technology Development Dept. in the Design Technology Div. at Renesas Technology Corp. “We have used Virtuoso technology for analog and mixed-signal designs for years and expect great results with our deployment of Virtuoso IC 6.1 at our worldwide design sites.”
The constraint-driven methodology enabled by Virtuoso IC 6.1 technology can ease the way for IP reuse, while its constraint-driven verification capability can cut the time needed to ensure design intent is maintained.
Renesas cited the Virtuoso technology’s advanced automation, including its yield optimization, parasitic-aware design mode and constraint template features as being extremely useful. Renesas engineers are using the constraint template to develop complex constraints for layout automation. The company’s use of SKILL-based process design kits (PDKs) allows for more complex Pcells and faster design time with high-quality results.
“Cadence and Renesas have had a long relationship when it comes to using Virtuoso," said Tom Beckley, corporate vice president at Cadence. “We are pleased that Renesas has both seen and verified the value of our IC 6.1 offering and are now deploying it successfully throughout their design groups."
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
|
Cadence Design Systems, Inc. Hot IP
Cadence Design Systems, Inc. Hot Verification IP
Related News
- UMC and Cadence Collaborate on Analog/Mixed-Signal Flow for 22ULP/ULL Process Technologies
- Cadence and UMC Collaborate on Certification of Analog/Mixed-Signal Flow for 28HPC+ Process
- Hitachi Adopts Cadence AMS Model-Based Methodology and Tools for Mixed-Signal Design Verification
- Kandou Uses Cadence Analog/Mixed-Signal Timing and Power Signoff Tools to Deliver High-Speed SerDes PHY IP Design on 28nm Process
- Cadence Receives Two TSMC Partner of the Year Awards for 10nm FinFET Solutions and Analog/Mixed-Signal IP
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |