Dolphin Integration announces the availability of a complete FREE evaluation kit for its Memory CACHE controller
Meylan, France – January 29, 2010. Dolphin Integration announces the availability of a complete FREE evaluation kit for its Memory CACHE controller. Its name I-Stratus-LP stands for its position at level L1 as Instruction Cache for any processor in search for Low-Power.
Indeed, the breakthrough innovation of I-Stratus-LP is twofold: its dynamic adaptation to the program demands through self-reconfiguration ensuring a drastic reduction of power consumption.
The gains provided by I-Stratus-LP are outstanding:
- the power consumption may be divided up to 12 times
- the apparent frequency may be up to 4 times accelerated
Such results have been assessed with the HideBench benchmark applied on an 8051 in 0.18 um process.
Do not wait anymore: ask for your FREE evaluation of I-Stratus-LP, to appreciate the gain provided by this cache in your own system!
Send an E-mail to logic@dolphin.fr and play with all the parameters of the kit!
It includes an instance of a couple MCU + its program memory and the HideBench benchmark. For a deeper appreciation of I-Stratus-LP in your system, you can simply change the parameters of the program memory and run your own benchmark!
About Dolphin Integration
Dolphin Integration is up to their charter as the most adaptive creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation and Foundry independence. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components, resilient to noise and drastic for low power-consumption, together with engineering assistance and product evolutions customized to their needs.
For more information about Dolphin, visit: www.dolphin.fr/rock
|
Dolphin Design Hot IP
Related News
- HiTrend selects Dolphin Integration's cache controller for its next generation of smart energy metering chips
- The new platform "MyDolphin" for free evaluation kits of Dolphin Integration's libraries
- Dolphin Integration announce the availability of their Reusable Power Kit Library at TSMC 180 nm eLL
- Dolphin Integration launches new AHB compliant Cache controller to meet growing demand for both energy efficient and faster SoC with NVM
- The art of embedding Non-Volatile Memories renewed by Dolphin Integration's Cache
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |