ARM to detail power-efficient design technique

Dylan McGrath, EE Times
(02/09/2010 10:04 AM EST)

SAN FRANCISCO—Using a hybrid technique for dynamic detection and correction of timing errors, researchers from ARM Holdings plc and the University of Michigan have demonstrated a 52 percent reduction in power on a 65-nm ARM instruction set architecture (ISA) processor running at more than 1 GHz, according to a paper scheduled to be presented at the International Solid State Circuits Conference (ISSCC) here Tuesday (Feb. 9).

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