Eureka Technology Supports PLB Bus Interface for Most of Its Popular IP Cores
Los Altos, California, February 11th, 2010 - Eureka Technology, a leading provider of system connectivity IP cores for SoC and FPGA designs, today announces the availability of the CoreConnect™ PLB™ Bus interface option for most of its IP core products. PLB Bus is the native interface standard for PowerPC and Power Architecture-based embedded processors and the Xilinx MicroBlaze™ CPU. By supporting the PLB™ bus interface standard, Eureka’s IP cores can be integrated seamlessly with any SoC design based on these standard CPU cores.
"Eureka Technology has a large selection of features rich IP cores designed for SoC and FPGA implementations," said Simon Lau, president of Eureka Technology. "Most of our IP cores such as SD/MMC controllers and NAND Flash memory controllers already support a wide selection of bus interfaces including AXI, AHB, APB, Wishbone, Avalon, and SH4 buses. The addition of PLB bus interface enables us to address virtually all our customers’ interface design needs from a single source."
Adding the PLB bus interface option to the wide variety of IP cores offer by Eureka Technology creates endless combinations of bridge applications for its customers. A sample of such designs include PLB to AHB bridge, PLB to PCI bridge, PLB to Wishbone bridge, or PLB SD controller in addition to PLB-based SDRAM controller, DMA and NAND Flash controllers. These IP cores feature PLB slave and PLB master as required. All of these IP cores can be implemented in any SoC and FPGA technology. These cores are available immediately in Verilog, VHDL, and FPGA netlist formats.
About Eureka Technology
Eureka Technology Inc. is a leading Intellectual Property (IP) core provider to ASIC/SoC, FPGA and system designers. The company develops and markets innovative IP cores that enable its customers to create and produce differentiating products. Eureka offers a wide range of silicon proven system core logic and peripheral functions to be used with different CPU and peripheral bus standards including PLB™, AXI™, AHB™, PowerPC™, PCI Express™, PCI™, Cardbus™, SDR/DDR SDRAM, NAND Flash, SD memory™, SDIO™, MultiMedia Card (MMC) CompactFlash™ and PCMCIA™. These IP cores offer advanced features, allowing customers to create product differentiation while improving time-to-market and reducing development costs. Located in the heart of Silicon Valley, California, Eureka Technology has licensed hundreds of IP cores to leading semiconductor and system companies worldwide. For additional information on the company and product offerings, please visit our website at http://www.eurekatech.com or send an email to info@eurekatech.com.
|
Eureka Technology Hot IP
Related News
- High Performance DDR3 SDRAM Controller from Eureka Technology Supports AHB and AXI Bus Interface.
- Eureka Technology IP Core Supports NASA's MARS 2020 Perseverance Rover Mission
- Intel joins CHIPS Alliance to promote Advanced Interface Bus (AIB) as an open standard
- New Version of Most Widely Used Camera and Imaging Interface - MIPI CSI-2 - Designed to Build Capabilities for Greater Machine Awareness
- The DTPCI32DC - Dual Clock 32bit PCI Bus Target Interface from Digital Core Design
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |