Intelop corporation's TCP Offload engine IP delivers amazing TCP/IP throughput
Intelop corporation’s TCP Offload engine IP delivers amazing TCP/IP throughput as reported by customers in system level performance testing. This second generation Customizable Full TCP offload Engine also integrates GEMAC, ARP module, RDMA engines, PLB/405 bus interfaces running at 2-Gbps. It is capable of implementing/ accelerating hundreds of simultaneous TCP sessions, delivering 800 % -1500% performance improvement over TCP/IP software implementations.
Santa Clara, California – Feb 16, 2010. Intelop Corporation, a leading high-end IP developer, customization & electronic engineering design services provider, today announced performance results for their TCP offload engine SoC IP when tested with a networking application in a real networking system after getting validation from their customers.
The performance data is available upon request. Customer’s name is not released due to NDA terms.
It is the only TOE engine that allows customers to customize TCP/IP related differentiated features and integrates so many other functions in hardware. All of TCP-connection related tasks, TCP-Payload transfer tasks, TCP-disconnection, TCP-session management overhead which traditionally is performed by TCP/IP software is accomplished by the hardware engines in TOE resulting in an order magnitude performance improvement. It is a new paradigm and new level of integration in networking hardware acceleration.
Because of its advanced scalable architecture, it can be customized to implement differentiated features and performance requirements to meet customer’s specifications e.g. misc. protocol processing and monitoring at G-bit line rate, in addition to TCP/IP, ARP module, number of simultaneous connections, TCP/IP performance tuning based upon type of network/traffic and application usage, scalable packet FIFO size, scalable size of Session Management table, Session Parameters, scalable size of direct store Packet memories, integrated DDRn/SSRAM controllers (optional), choice of PHY interface - GMII or Serial and more.
This Integrated TOE SoC silicon IP with customizable features provides enhanced functionality in all networking equipment including; Layer-2-5 Switches/Routers, IPS/IDS appliances and Network Security appliances, Severs and high end NICs. Advanced architecture with built in scalability allows customers to target it to many silicon libraries from FPGAs to 0.18 um-0.090 nm ASIC or SOC without compromising performance or functionality.
“We utilized our expertise in designing highly successful and advanced technology Multi-Giga bit Networking equipment, Enterprise-class IDS/IPS, Network Security appliances employing SOCs also designed by intelop in defining the architecture of this TOE engine,” said K Masood. “We are excited about this new crown jewel and the ability to develop value-added leading edge network acceleration IPs and total solutions for our customers.” said Kevin Moore of Intelop.
Intelop Corporation is a custom IP developer, SoC/ASIC/FPGA integrator and engineering services provider for Networking, Network Security, Network/storage and Embedded Systems. They offer silicon proven semiconductor IP and services with comprehensive hardware and software experience. http://www.intelop.com
|
Related News
- Intilop (formerly Intelop) corporation's TCP Offload engine IP solution delivers amazing TCP/IP throughput as reported by customers in system level performance testing
- Intilop TCP Offload Engine Delivers Full TCP Offload in Less than 100 nanoseconds Using Altera's Stratix IV FPGA
- Intilop's TCP/IP Offload engine provides lowest latency and fastest TCP/IP throughput
- Intelop announces industry's first customizable TCP-Offload Engine at 2-Gpbs with integrated Ethernet MAC Silicon IP for SOC, ASIC and FPGA customers in Network equipment, Network Security, Telecom, SAN/NAS markets
- Intilop delivers their enhanced Dual 10G iNICs with Ultra-low latency TCP and UDP Offload accelerators, benchmarking sub micro second wire-to-host latency and Ultra high data throughput
Breaking News
- Arm loses out in Qualcomm court case, wants a re-trial
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
Most Popular
E-mail This Article | Printer-Friendly Page |