Magillem introduces Rev.Enge, the first platform tackling the obsolescence issue in the electronic CAD flow
Magillem leverages on its expertise on the IEEE 1685 IP-XACT specification.
Paris, February 26, 2010 -- Managing the life cycle of an equipment including numerous hardware and software components is a headache for every manufacturer, and one that cannot be discounted as it impacts complex and expensive systems with long term customer contracts : the financial stakes are high. In many cases, safety and security of the equipment must be guaranteed thru a very tedious and demanding certification process (we are thinking nuclear, aero space, transportation, energy, military, medical systems). The simple replacement of a component implies months or even years of re-certification, at a significant cost. The challenge is all the more baffling that one must reconcile a shorter and shorter component life – a 4 year average - with the life span and maintenance term of electronic systems exceeding 10 or 15 years. This is problematic too for software modules, which are very difficult to maintain on the long term.
Capitalizing from its strong experience in the methodology used to assemble designs by using metadata description of intellectual property blocks and components, Magillem is introducing a new line of products targeted towards systems integrators.
Rev.Enge captures and traces all the information on your designs. A true mapping of a complex system specified in a descriptive meta model, with all the relationships, dependencies, attributes, parameters, files location, but independent from the various tools and data formats used for the design, will preserve the life term of the system beyond the one of its parts.
Cyril Spasevski, Chairman and CTO of Magillem Design Services, says:”Our customers reuse designs, IP blocks, platforms and sub-systems and they rely on us to provide a comprehensive set of tools to help them with methodology issues. In addition to our integrated development environment, Rev.Enge provides the layer and the monitoring tools needed for obsolescence management. Reuse, refit, and redesign: it all aims at saving time and money in the long run by keeping the flow and the systems independent from tools, components and CAD vendors while maintaining quality and innovation in a rapidly changing industrial market place.
Previous attempts at supporting the engineering process with a connected set of information are merely relational data bases in a proprietary format with no dynamic and certainly not based on a structural schema.
Within the description of the platform, Rev.Enge allows the designer to:
- integrate the requirements of the projects through the hierarchy
- verify the following of the requirements
- manage the changes of the requirements
- Maintain the traceability of these requirements
This methodology guaranties consistency, coherency and the traceability of the platform requirements all along its life cycle.
During the design or re-fit of a platform it is crucial to follow a reliable path of development which promotes the long term viability of a machine in the field. Linking the specifications and the architecture of the platform, Rev.Enge offers a complete solution based upon the open standard IEEE 1685 IP-XACT with the following objectives:
- Facilitate the propagation of the characteristics (timing, time constraints, and operation security constraints) through the hierarchy
- Reassemble blocks or sub systems to meet original specification
- Guaranty a high level of quality and reliability by controlling the process of the platform design
- Guaranty that data will never be captive of a proprietary tool format
Using Oracle’s AUTOVUE©, as a generic viewer, Rev.Enge will show every single 2D or 3D CAD electronic or mechanical format of any system. Verification of platform assembly, constraints, requirements etc is for the first time independent from data formats, part vendors, tool vendors, languages.
Interface with software through the registers is also described and controlled, a unique capability that no one offers to this day.
Main benefits include:
- Improving independence from CAD tools vendors
- Improving interoperability, communication
- Benefiting from better user interfaces to raise productivity
- Relying on worldwide adopted standards
- Automation of valueless and repetitive steps
- Saving time and money
- Avoiding error-prone information exchange at interfaces
- Increasing process reliability
- Extending the life span of systems
- Enabling cost effective potential innovations in existing systems
About Magillem
Not just another EDA vendor, Magillem is an enabler of production level IP-Reuse- based design method and the leading provider of IEEE 1685 (IP-XACT) compliant tools and services. Magillem has developed an easy to use, state of the art platform solution to cover electronic systems design flow challenges in a context where complexity, interoperability and design re-use are becoming critical issues to manage design cycle time of SOC. Magillem Design Services SA was established in November 2006 and privately funded by a group of 8 co-founders: engineers and business angels.
Company is headquartered in Paris, France, with offices in Bristol, UK, New York, USA, and Tokyo, Japan.
Magillem has a long list of first tier active customers: Texas Instrument, Qualcomm, ST Microelectronics, NXP (ex- Philips semiconductors), ST-ERICSSON, Sonics, ESA, CEA, Thales, Thomson, and EADS …
Magillem is a public company traded on the Euronext Free Market. For further information please visit www.magillem.com.
About IEEE 1685 (IP-XACT)
IP-XACT is an undisputed worldwide XML format that defines and describes electronic components and their designs. IP-XACT was created by the SPIRIT Consortium, now part of Accellera, as a standard to enable automated configuration and integration through tools. 120 industrial companies and organizations are members! The goals of the standard are:
- to ensure delivery of compatible component descriptions from multiple component vendors,
- to enable exchanging complex component libraries between electronic design automation (EDA) tools for SoC design (design environments),
- to describe configurable components using metadata, and
- to enable the provision of EDA vendor-neutral scripts for component creation and configuration (generators, configurators).
For further information please visit www.magillem.com.
|
Related News
- Magillem announces that Magillem Platform Assembly solution is now supporting OCP Vendor Extension for IEEE 1685 IP-XACT
- Magillem promotes IP Reuse, interoperability through IEEE 1685 and launches its IP-XACT Checkers Suite Software and Compliance Lab
- Sonics Eases SoC Design Flow Integration Using Magillem IP-XACT Checker Suite
- Magillem launches Rev.Enge 2.0, the ultimate design capture solution for PCB/FPGA/ASIC/FIRMWARE development, 3 new plug-ins in this release addressing Technical Documentation Flow, Legacy Formats or Designs, and Certification
- Accellera and the IEEE Standards Association Report on Popularity of Intellectual Property (IP) Standard
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |