Dolphin Integration announces the availability of a brand new Front End generator: spRAM Haumea for the 130 nm G process
Meylan, France – March 26, 2010. Dolphin Integration’s strategy for the 130 nm technological process is to release a Register Bank Panoply for SoC designers with the capability to generate instances from 1 bit up to 512 kbits.
The Register Bank Panoply includes:
- Synthetizable instances with the SESAME Library of Reduced Cell Stems optimized for High Density (HD-BTF) and for High Speed (HS-BTF) with the smallest capacities of the Panoply, enabling FIFOs, etc.
- Generated instances with the one-port Register File Aura architecture optimized for high speed and high density for medium capacities.
- Generated instances with the Single metal programmable sROMet Cassiopeia optimized for low consumption both dynamic and static.
- Generated instances with the SPRAM Haumea architecture optimized for low dynamic power and density for largest capacities.
The first element of the 130 nm Register Bank Panoply releasesd is the generator for the spRAM Haumea. The Haumea architecture represents the best mix between Power Consumption and Density:
- The spRAM Haumea meets the most demanding power budgets thanks to its smart low power design and its power reduction features: data retention mode, stand by mode, byte write.
- The spRAM Haumea also allows cost reduction thanks to its high-density architecture: depending on the capacity, Haumea is up to 10% denser than free alternative solutions.
The Haumea generator available on Dolphin Integration website for the SMIC 130 nm G process offers flexibility from 32 kbits up to 512 kbits.
For more information about Haumea: http://www.dolphin.fr/flip/ragtime/013/ragtime_013_ram.html
About Dolphin Integration
Dolphin Integration is up to their charter as the most adaptive creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation and Foundry independence. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components, resilient to noise and drastic for low power-consumption, together with engineering assistance and product evolutions customized to their needs.
For more information about Dolphin, visit: www.dolphin.fr/sesame
|
Dolphin Design Hot IP
Related News
- Dolphin Integration announces the availability of the new generation 28 nm SpRAM generator
- Dolphin Integration announces the availability of the new generation of SpRAM generator at 90 nm and 55 nm eFlash
- Availability of Dolphin Integration's TSMC-sponsored ROM at the 130 nm BCD 5 V process
- Dolphin Integration announces the availability of the new generation of Foundry Sponsored SpRAM generator at 55 nm
- Dolphin Integration breakthrough innovation for TSMC 180 nm BCD Gen 2 process: Up to 30% savings in silicon area with the new SpRAM RHEA
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |