Faraday Launches Its USB 3.0 PHY in UMC 90nm

Small die size with low power consumption enables customers' SoC design

Hsinchu, Taiwan, March 30, 2010 -- Faraday Technology Corporation (TAIEX: 3035) today announced the availability of its commercial USB 3.0 physical layer (PHY) at UMC 90nm high-speed (HS) process. With smaller size and lower power consumption than peers', this new component is developed based upon USB 3.0 version 1.0 specification functionally and electrically, achieving the maximum speed of 5.0Gbps.

With the well-known advantages of being backwards compatible with over 10 billion USB devices shipped to-date, and enabling up to 10 times faster connections, USB 3.0 seems poised to become the most pervasive high-speed connectivity technology over the coming years. However, it also brings the concern about its ascending power consumption and die size, especially while targeted on some portable and consumer electronic devices. Succeeding to the remarkable launch of USB 3.0 in UMC 0.13um as the early pioneer, Faraday, keeping its improvement in the design architecture to reduce power consumption and die size, successfully delivers USB 3.0 PHY in UMC 90nm with relatively lower power consumption than other competitors.

"I am excited to announce the availability of our USB 3.0 PHY in 90 nm soon after the one in 0.13um," said Steve Wang, Chief Strategy Officer at Faraday. "For the 0.13um version released in May, 2009, we have got market success in both host and device sides with mass production of mother board, express card, external HDD and flash storages. We believe the newly launched PHY in 90 nm with even lower power consumption and smaller die size can further assist our customers to implement their sophisticated SoC designs such as printer, surveillance, server and handheld applications, " he added.

To achieve the target of low power design in 90nm, Faraday has carried out certain sophisticated improvement in the PHY architecture, including a regulated PLL structure to reduce design corners. Further, Faraday introduced a dual-loop half-rate structure for CDR and adopted the active peaking method to increase the effective bandwidth for transmitter to meet 5Gbps data rate with lower current consumption.

"We are pleased to demonstrate our design capability by USB 3.0 in 90nm," said Y.K. Tseng, Associate Vice President at Faraday. "We have accumulated a lot of experience in high-speed IO design and will continue to provide competitive solutions to our customers. UMC 0.11um aluminum and 55nm will be our next milestones with the hope of comprehensive USB 3.0 IP offerings to satisfy customers' demand in terms of cost competitiveness, stability, and performance. ”

Availability

Faraday's USB 3.0 PHY in UMC 90nm is now available, and will be shown in USB Devcon on April 1st and April 2nd in Taipei.

About Faraday Technology Corporation

Faraday Technology Corporation is a leading fables ASIC and silicon IP provider. The company's broad silicon IP portfolio includes Cell Library, Memory Compiler, ARM-compliant CPUs, DDRI/II/III, MPEG4, H.264, USB 2.0/3.0, 10/100 Ethernet, Serial ATA, and PCI Express. With 2009 revenue of US$ 160 million, Faraday is one of the largest fabless ASIC companies in the Asia-Pacific region, and it also has a significant presence in other world-wide markets. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. For more information, please visit: www.faraday-tech.com

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