MoSys Exhibits at TSMC Tech Symposium
Apr 09, 2010 -- MoSys, Inc.:
Who:
MoSys (NASDAQ: MOSY), a leading provider of differentiated, high-density memory and high-speed interface (I/O) intellectual property (IP), will be exhibiting at TSMC's 2010 Technology Symposium.
What:
The TSMC 16th Annual Technology Symposium brings together the best and brightest in the global semiconductor industry to "Collaborate to Innovate."
Where/When:
San Jose, CA - Tuesday, April 13 (8 a.m. - 5 p.m.)
San Jose McEnery Convention Center
150 West San Carlos Street
San Jose, CA 95110
Austin, TX - Friday, April 16 (8 a.m. - 5 p.m.)
Four Seasons Hotel
98 San Jacinto Blvd
Austin, TX 78701
Boston, MA - Tuesday, April 20 (8 a.m. - 5 p.m.)
Westin-Waltham Hotel
70 Third Avenue
Waltham, MA 02451
More information is available on MoSys' website at http://www.mosys.com/eventCalendar.php
About MoSys, Inc.
Founded in 1991, MoSys(R) (NASDAQ: MOSY), develops, markets and licenses differentiated embedded memory and high speed parallel and serial interface IP for advanced SoC designs. MoSys' patented 1T-SRAM(R) and 1T-Flash(R) memory technologies offer a combination of high density, low power consumption, high speed and low cost advantages that are unmatched by other available memory technologies for a variety of networking, computing, storage and consumer/graphics applications. MoSys' silicon-proven interface IP portfolio includes DDR3 PHYs, as well as SerDes IP that support data rates from 1 Gigabit per second (Gbps) to 11 Gbps, across a wide range of standards, including PCI Express, XAUI, SATA and 10G KR. MoSys IP has been production-proven in more than 225 million devices.
MoSys is headquartered in Sunnyvale, California. More information is available on MoSys' website at www.mosys.com.
|
Related News
- EDA toolset parade at TSMC's U.S. design symposium
- TSMC Celebrates 30th North America Technology Symposium with Innovations Powering AI with Silicon Leadership
- Credo at TSMC 2024 North America Technology Symposium
- Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium
- U.S. Subsidy for TSMC Has AI Chips, Tech Leadership in Sight
Breaking News
- JEDEC® and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard: Advancing Bandwidth, Efficiency, and Capacity for AI and HPC
- BrainChip Gives the Edge to Search and Rescue Operations
- ASML targeted in latest round of US tariffs
- Andes Technology Celebrates 20 Years with New Logo and Headquarters Expansion
- Creonic Unveils Bold Rebrand to Drive Innovation in Communication Technologies
Most Popular
- Cadence to Acquire Arm Artisan Foundation IP Business
- AMD Achieves First TSMC N2 Product Silicon Milestone
- Why Do Hyperscalers Design Their Own CPUs?
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- New TSN-MACsec IP core for secure data transmission in 5G/6G communication networks
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |