Aldec Adds RMM Library and FPGA Primitive Support to ALINT
HENDERSON, Nev.-- April 19, 2010 --Aldec Incorporated, a leader in RTL Simulation and Electronic Design Automation (EDA), announces today its latest Design Rule Checking application, ALINT™ 2010.02. The release adds support for Reuse Methodology Manual (RMM) design rules that define a methodology for efficient reuse and verification of System-On-A-Chip (SoC) designs. Altera® and Xilinx® FPGA vendor primitives are now supported to enable accurate design rule checking on the latest FPGA devices. For a complete description of all enhancements refer to the What's New presentation.
ALINT is Design Rule Checking software for fast design closure. The software analyzes and detects issues early in the design and verification cycle of complex ASIC, FPGA and SoC designs. The latest release includes advanced technology enabling detection of all the levels of RTL design issues – starting from comparatively simple naming conventions and design structure to advanced topics such as reuse, optimal synthesis, power and area consumption, Design-For-Test (DFT), and Clock Domain Crossings (CDC).
Availability
ALINT 2010.02 is available today and sold directly from Aldec and its authorized worldwide distributors. The product offers support for RMM, STARC, DO-254 and Aldec design rule plug-ins, which are sold separately. For more product information or to download a free evaluation copy, visit www.aldec.com
About Aldec
Aldec Incorporated is an industry-leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.
|
Related News
- Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM Enhancements
- EnSilica adds Post Quantum Cryptography support to eSi-Crypto IP library
- Gowin Semiconductor Adds Ubuntu Support to their Gowin EDA FPGA Software for Improved Artificial Intelligence and IoT Development Toolchain Integration
- Lattice Diamond 3.11 Software Adds Support for New MachXO3D FPGA
- Flexras Technologies Enhances Wasga Compiler Partitioning Tool, Adds Support for Virtex-7 FPGA-based FPGA Platforms
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |