Calypto Extends Industry Lead in RTL Power Optimization
Mode-Based Design Optimization, Enhanced Usability Features Further Reduce Power and Improve Design Team Efficiency
SANTA CLARA, Calif. – June 8, 2010 – Calypto Design Systems Inc., the leader in sequential analysis technology, today announced the release of PowerPro 4.0, the latest version of the industry’s most advanced RTL power optimization product family. Providing sweeping improvements to PowerPro CG, PowerPro MG and PowerPro Analyzer, PowerPro 4.0 offers enhanced power optimization and usability features, enabling designers to deliver the lowest power designs possible in the shortest amount of time. PowerPro 4.0 will be showcased next week at the 47th Design Automation Conference in Anaheim.
“Working closely with the world’s leading electronic systems and SoC suppliers, we continue to improve the user experience of PowerPro while delivering greater power reduction capabilities,” said Tom Sandoval, Calypto’s chief executive officer. “The advancements in PowerPro 4.0 will enable our customers to deliver the most power optimized solutions possible in the shortest amount of time with the least amount of effort.”
PowerPro CG, Calypto’s sequential clock gating power optimization tool for RTL designers, now performs mode-based optimizations, enabling the tool to implement additional sequential clock gating for maximum power savings. Mode-based power optimizations have delivered up to 3X power savings beyond what was previously possible. PowerPro CG also features new innovative enable expression optimization and switching activity propagation capabilities, improving runtimes by up to 2X.
The advancements in PowerPro MG (for automated RTL memory power optimization) allow users to easily identify memory BIST and ECC logic to the tool, enabling PowerPro MG to find additional memory gating opportunities that can deliver up to 50 percent additional power savings. This new feature also reduces the effort required by designers to optimize both dynamic and leakage power dissipated by on-chip memories.
PowerPro 4.0 also includes a new version of PowerPro Analyzer delivering more accurate power analysis based on new sequential analysis techniques to accurately propagate switching activity. The new PowerPro Analyzer also features expanded power reporting capabilities specifically to enable greater power savings using the PowerAdviser flow. Using sequential design information generated by PowerPro CG and PowerPro MG, the PowerAdviser Flow provides users with specific design changes that can be manually implemented in their RTL code to reduce power.
Pricing and Availability
Calypto’s PowerPro 4.0 runs on PC platforms running Linux. PowerPro CG and PowerPro MG are each priced at $295K for a one-year, time-based license. PowerPro Analyzer is included with either PowerPro CG or PowerPro MG.
Calypto Showcases PowerPro 4.0, SLEC Products at DAC
Calypto will be at the 47th DAC June 14-18th in booth #286, showcasing their entire suite of power optimization and formal verification tools. To register for a private demonstration visit: www.calypto.com/events.php.
Additionally, Calypto will present at the panel titled, “What input language is the best choice for high level synthesis?” to be held at 4:30 p.m. on Thursday, June 17th in room 207AB.
About Calypto
Founded in 2002, Calypto Design Systems, Inc. empowers designers to create highquality, low-power electronic systems by providing best-in-class RTL power optimization and functional verification software, based on its patented sequential analysis technology. Calypto, whose customers include Fortune 500 companies worldwide, is a member of the Cadence Connections program, the IEEE-SA, Synopsys SystemVerilog Catalyst program and the Mentor Graphics OpenDoor program. Calypto has offices in Europe, India, Japan and North America. Corporate headquarters is located at: 2933 Bunker Hill Lane, Suite 202, Santa Clara, Calif. 95054. Telephone: (408) 850- 2300. More information can be found at: www.calypto.com.
|
Related News
- Real Intent and Calypto Partner to Offer Best-in-Class Integrated Tool Flow for RTL Power Optimization and Sign-Off
- Xilinx ISE Design Suite 12.3 Introduces AMBA 4 AXI4 IP Cores, Enhances PlanAhead Design and Analysis Cockpit, Extends Power Optimization
- Calypto Delivers Industry's First Automated Tool for Memory Power Optimization
- Cadence Extends Low-Power Leadership With Early Dynamic Power Analysis and Pre-RTL Exploration
- Siemens extends leadership in EDA design-for-test with the launch of Tessent RTL Pro
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |