Dolphin Integration introduces an ultra High Density Library decreasing the 130 nm logic area up to 30%
Meylan, France – June 11, 2010. Designers of cost-optimized SoC designs can rely upon the highest-density Standard Cell Library, HD-BTF to improve the area of their logic blocks with a decrease up to 30%.
Compared with typical 9 tracks library after P&R, HD-BTF make easier the quest for density:
- 6 track library
- High Density flip flop: the Spinner cell system for reduced sequential area
- Density optimized cell layout and placement of pins
- Delivered with optimization scripts for each stage of the implementation flow: from Synthesis, through Placement and construction of the Clock paths to Routing.
Density remains the Holy Grail for many SoC Integrators, but they tend to rely on stale scripting techniques. Indeed, from the 130 nm process node, the increasing complexity and size of logic blocks forces SoC integrators to concentrate more than ever on tuning their designs with high leverage. This challenge is even more noticeable for applications with high fabrication volumes such as mobile phones. Achieving a cost effective SoC by embedding a “cost-cutting” Library is now the last frontier.
More information on the key benefits and performances of HD-BTF is available directly on the link below: http://www.dolphin.fr/flip/sesame/013/sesame_013_products.html
Benchmarking this Standard Cell Library against any other now is easy with the Sofia Benchmark and the Motu Uta public standard, visit our website:http://www.dolphin.fr/flip/sesame/sesame_benchmark.php
or contact sesame@dolphin.fr
A High-Density Panoply including a complete solution for all elements of the logic design is also available to address the cost reduction challenge at the architectural level.
The panoply includes Single Port and Dual Port RAMs, metal programmable ROMs, Register Files and standard cells.
About Dolphin Integration
Dolphin Integration is up to their charter as the most adaptive creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation and Foundry independence. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components, resilient to noise and drastic for low power-consumption, together with engineering assistance and product evolutions customized to their needs. For more information about Dolphin, visit: www.dolphin.fr/sesame
|
Dolphin Design Hot IP
Related News
- Dolphin Integration introduces a new Panoply of Silicon IPs for reducing the 65 nm silicon area up to 10%
- Dolphin Integration enable Dongbu HiTek's users to benefit from their ultra high density standard cell library
- Dolphin Integration launches a standard cell library with ultra-high density up to 30% savings
- Dolphin Integration breakthrough innovation for TSMC 180 nm BCD Gen 2 process: Up to 30% savings in silicon area with the new SpRAM RHEA
- Ultra high density standard cell library SESAME uHD-BTF to enrich Dolphin Integration's panoply at TSMC 90 nm eF and uLL
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |