TSMC New Standard Cell Slim Library Reduces Logic Area 15%
First Library Introduced Under AreaTrim Collaboration with Tela Innovations
HSINCHU, Taiwan, R.O.C., June 15, 2010 -- Taiwan Semiconductor Manufacturing Company, Ltd. today introduced the first Slim Library that reduces system-on-chip (SoC) routed logic block area by 15 percent compared to blocks routed through current standard cell libraries.
The library targets TSMC's 65nm LP process technology and fits existing implementation flows for easy adoption. Designers can use the new Slim Library in existing or new designs without change to design tools and implementation methodologies.
Slim Library is the result of the AreaTrim™ design and process co-optimization program between the TSMC and Tela Innovations. The library is based on Tela's patented layout style and TSMC's process optimization. The two companies demonstrated the 15% area improvement through synthesis and timing-driven place and route implementations on multiple versions of widely used microprocessor cores.
The new library's layout style draws a lithography-optimized pattern with uniform density through unidirectional poly on a fixed pitch and improved manufacturing process control to reduce area. As a result, Slim Library achieves gate densities of up to 1 million gates per square millimeter.
Slim Library is re-designed into 8 tracks from the traditional 9-track configuration, yet provides equivalent performance and power. The library includes Multiple Vt options and power management cells along with full set of characterization corners.
"The Slim Library is an excellent example of TSMC's commitment to collaborate with it ecosystem partners to create differentiated value," said ST Juang, senior director of Design Infrastructure Marketing at TSMC. "The AreaTrim program is an outgrowth of TSMC's Open Innovation Platform™ and proof that we will continue to provide expanding family of innovative products."
Availability
The new 65LP Slim Library is available now in limited release through the TSMC Online customer design portal (http://online.tsmc.com/online) or by contacting local TSMC account management or support representatives. General release is targeted for the first quarter of 2011.
About TSMC
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry's largest portfolio of process-proven libraries, IPs, design tools and reference flows. The Company's managed capacity in 2009 totaled 9.96 million (8-inch equivalent) wafers, including capacity from two advanced 12-inch GIGAFABs™, four eight-inch fabs, one six-inch fab, as well as TSMC's wholly owned subsidiaries, WaferTech and TSMC China, and its joint venture fab, SSMC. TSMC is the first foundry to provide 40nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please visit http://www.tsmc.com.
|
Related News
- Dolphin Integration measures 15% area reduction on 65 nm logic circuit with its 6-Track standard cell library
- Save up to 20 % of silicon area with Dolphin Integration's standard cell library SESAME uHD
- Dolphin Integration introduces a new Panoply of Silicon IPs for reducing the 65 nm silicon area up to 10%
- 90% Reduction in power consumption for RFID chips with Dolphin Integration's SESAME eLC standard cell library
- Ultra high density standard cell library SESAME uHD-BTF to enrich Dolphin Integration's panoply at TSMC 90 nm eF and uLL
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |