FPGA startup Tier Logic folds
Dylan McGrath
7/22/2010 3:16 PM EDT
SAN FRANCISCO—Tier Logic Inc., a programmable logic startup developing a novel processing technology to build FPGA and ASIC products on a single die, has folded, EE Times has learned.
TierLogic (Santa Clara, Calif.) shut down operations last week, unable to find funding for a series B round, according to Paul Hollingworth, Tier Logic's vice president of sales and marketing.
"Despite the fact that we had only spent less than $20 million, we couldn’t get a lead investor to come in to a series B funding round," Hollingworth wrote in an email to EE Times.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Related News
- Logic Fruit Technologies Elevates FPGA Innovation with AMD Xilinx Premier Partnership
- Logic Design Solutions Launches NVME Host IP on Xilinx Ultrascale & Ultrascale Plus FPGA
- Logic Design Solutions Introduces the first NVMe HOST IP on POLARFIRE SoC FPGA
- Achronix and Logic Fruit Introduce IP Solutions for Test and Measurement Applications
- Xilinx Announces the World's Largest FPGA Featuring 9 Million System Logic Cells
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset