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Adaptive Clock Generation Module for DVFS and Droop Response
Mentor moves tools toward 16-nanometer
Ron Wilson, EETimes
8/23/2010 3:51 PM EDT
A conversation last Friday (Aug. 20) with Joseph Sawicki, vice president and general manager of the Mentor Graphics Corp.'s Design to Silicon Division, provided a snapshot of the conundra facing foundries and EDA vendors as they approach sub-20-nm process geometries. The landscape is filled with uncertainties, Sawicki warned, but there is no time left to wait for resolution.
"We saw our first 16-nm test chips go out a couple of months ago," Sawicki said in an interview Friday (Aug. 20). "There is design work going on now at that node—so far, though, it is mostly intellectual-property development."
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