The future of SoC verification: Enterprise computing?
Ron Wilson, EETimes
8/26/2010 6:10 PM EDT
Perhaps the world of SoC verification gives the appearance of gradual and organized development. But the real story, as it emerges from an interview last week with Mentor Graphics DVT Division general manager John Lenyo, looks more like the modern view of evolution: sporadic change along many different axes, driven not so much by a master plan as by the crushing and impersonal weight of every-growing complexity. Yet verification teams can, and must, manage that evolution.
Lenyo suggested a number of areas in which he saw shifts in SoC verification practice. Change is influencing the way design teams formulate design requirements. Shifts are also rippling through the process of verifying the design against those requirements and isolating bugs. And there is slow but irresistible change in the way teams manage data and assess the state of the verification process.
E-mail This Article | Printer-Friendly Page |
|
Related News
- SambNova Systems Announces $250 Million Series C as it Continues to Set a New Course for the Future of Enterprise Computing
- Cadence and Xilinx Simplify SoC Development With Enterprise Verification Capabilities for FPGA Targeted Design Platforms
- ESWIN Computing Pairs SiFive CPU, Imagination GPU and In House NPU in Latest RISC-V Edge Computing SoC
- MediaTek Joins Arm Total Design to Shape the Future of AI Computing
- Arm's Broadest Ever Automotive Enhanced IP Portfolio Designed for the Future of Computing in Vehicles
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models