AppliedMicro Picks Tensilica's Dataplane Processors for High-Throughput Communications Chip Design
Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)
SANTA CLARA, CA-- September 14, 2010 -- Tensilica,® Inc. today announced that AppliedMicro has selected Tensilica's Xtensa® LX dataplane processors (DPUs) for an upcoming high-throughput communications chip design project.
"We selected Tensilica's DPUs because of their remarkable ability to be customized with high-bandwidth, efficient interfaces, such as FIFO-like queues, to quickly stream data into and out of the processor," stated Sean Campeau, AppliedMicro's senior manager of engineering. "These high-speed connections bypass the main system bus altogether, allowing us to implement functions in the processor that previously could only meet our performance targets by being implemented in RTL (register transfer level) logic. Implementing these functions in a processor speeds our design effort considerably and gives us a much more flexible solution."
"AppliedMicro's project is typical of high performance dataplane signal processing designs that can take advantage of our customizable dataplane processor (DPU) and specialized I/Os," stated Steve Roddy, Tensilica's vice president of marketing and business development. "In the dataplane, our customers often need data throughput and computational performance that can't be achieved using traditional processors. With our unique and patented process of automated customization of dataplane processors, application-specific I/Os can be rapidly added to a processor core to meet any desired I/O bandwidth requirement."
About AppliedMicro
Applied Micro Circuits Corp. is a global leader in energy conscious computing solutions for telco, enterprise, data center, consumer and SMB applications. With a 30-year heritage as an innovator in high-speed connectivity and high performance embedded processing, AMCC, now AppliedMicro, employs patented transport and embedded processor SoCs to provide high performance energy efficient products. AppliedMicro's corporate headquarters are located in Sunnyvale, California. Sales and engineering offices are located throughout the world. For further information regarding AppliedMicro, visit the company's Web site at http://www.apm.com.
About Tensilica
Tensilica, Inc. is the leader in customizable dataplane processor IP cores. Dataplane Processor Units (DPUs) combine the best capabilities of CPUs and DSPs while delivering 10 to 100x the performance because they can be customized using Tensilica's automated design tools to meet specific signal processing performance targets. Tensilica's DPUs power SOC designs at system OEMs and six out of the top 10 semiconductor companies for products including mobile phones, consumer electronics devices (including digital TV, Blu-ray Disc players, broadband set top boxes, digital still cameras and portable media players), computers, and storage, networking and communications equipment. For more information on Tensilica's patented, benchmark-proven DPUs visit www.tensilica.com.
|
Related News
- 64-bit MIPS architecture provides low-power, high-throughput processing for Cavium's new OCTEON III processors
- Chelsio Communications Licenses Tensilica's Xtensa LX Customizable Dataplane Processor Core for 10 Gigabit Ethernet
- Blue Wonder Communications to Develop LTE Baseband IP Using Multiple Optimized Tensilica Dataplane Processors
- u-Nav Microelectronics Picks Tensilica's Xtensa Processors for Portable GPS Systems
- Phison Licenses Tensilica's Dataplane Processor (DPU) for NAND Flash Memory Controllers and SSD Applications
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models
Most Popular
E-mail This Article | Printer-Friendly Page |