Synopsys speeds Verilog, VHDL simulation

In the VCS 6.1 release, the speedups come from a new clock optimization technology. Ruiz said that it works by analyzing events that need to be processed by the simulator, and organizing them so that events can be more selectively evaluated. In addition to the speedup, the clock optimization technology allows VCS to use 30 per cent less memory, he said.

Ruiz said the company's "cross-compile" technology is an industry first. "Users probably have one or two large dedicated 64-bit servers, but they have a lot of investments in 32-bit workstations," he said. "Because they don't have to simulate on 64-bit workstations, they don't need to upgrade their verification environments."

The compile step presents the biggest capacity bottleneck, and hence the biggest need for 64-bit processing, Ruiz said. But VCS users can also simulate on 64-bit workstations if they choose, and Synopsys has optimized VCS for 64-bit platforms so there's no performance loss, he said.

VCS 6.1 also provides Synopsys' first support for the new Verilog 2001 standard. A switch allows backward compatibility with the previous 1995 standard.

The new Scirocco version 2001.10 lets users run cycle-based simulation for non-RTL blocks and for Vital library memory blocks, said Sylvie Hurat, product marketing manager for Scirocco. As a result, she said, the entire design can now be put into cycle simulation, as opposed to just synthesizable blocks.