Hitachi-STMicro venture deliver first 64-bit RISC core that runs at 700-Mips

Hitachi-STMicro venture deliver first 64-bit RISC core that runs at 700-Mips
By Semiconductor Business News
February 25, 2002 (11:43 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020225S0029

SAN JOSE, Calif. -- SuperH Inc., the joint chip venture between Japan's Hitachi Ltd. and Europe's STMicroelectronics Inc., here today announced its first product--a 64-bit RISC processor core that delivers 700 million of instructions per second (Mips).

Based on the SuperH family of RISC-based embedded processors, the SH5-100 is the world's first 64-bit CPU core, with a floating-point unit (FPU), single-instruction, multiple-data (SIMD) instructions and debug capabilities on the same device.

Ideally suited for system-on-chip (SOC) designs and embedded applications, SH-5 delivers in excess of 700-Mips at 400-MHz, while consuming less than 400mW. The core also offers backwards compatibility with earlier SuperH processors allowing customers to preserve their software investments.

The core is designed for set-top boxes, voice-over-Internet Protocol (VoIP) applications, graphics, games and car infotainment systems.

The SH-5 is available for licensing now as a hard or soft core along with various software and development tools. A range of design licenses are available from "perpetual to single-use," providing a variety of solutions to meet the needs of both designers and service providers, according to the San Jose-based venture.

"We've made it easy for customers to secure the right type of license to meet their development needs and ramp quickly to production," said Rick Chapman, vice president of marketing and sales of SuperH. Last year, STMicroelectronics and Hitachi announced plans to form an independent company to develop and license RISC microprocessor cores, based on the SuperH architecture (see April 3 story ).

Meanwhile, the core features a detachable IEEE-754 single- and double-precision FPU. The FPU is a co-processor contained within the general core and executes floating-point operations more quickly than the basic microprocessor.

It has separate floating-p oint registers that may be configured as 64-single precision, 32-double precision or 16-single precision vector registers. The FPU performs up to four multiply and three addition operations every clock cycle, achieving 2.8-GFLOPs at 400-MHz.

The SIMD core instructions operate on three operands, each of which may have eight 8-bit, four 16-bit or two 32-bit values. The core also features a so-called SHmedia mode, which is a complete 32-bit encoded fixed length instruction set that delivers multimedia performance with integer, packed arithmetic/SIMD and floating point operations. It is used for real-time applications where performance is at a premium.