LogicVision calls on 'ET' 4.0 to lower test costs for SoCs
LogicVision calls on 'ET' 4.0 to lower test costs for SoCs
By Semiconductor Business News
February 25, 2002 (12:26 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020225S0042
SAN JOSE -- LogicVision Inc. here today announced a new embedded software and hardware solution said to reduce the cost of test for system-on-a-chip (SoC) and other complex ICs. The product, dubbed Embedded Test 4.0 (ET 4.0), reduces silicon debug and diagnostics time in chip designs, thereby extending the life of existing automatic test equipment (ATE) or enabling the use of lower cost testers, according to San Jose-based LogicVision. ET 4.0 streamlines the process of architecting, implementing, and integrating an embedded test solution. It is also said to be the world's first product that enables a chip designer to design hierarchical test capability and seamlessly reuse it for silicon debug and manufacturing test. In addition, ET 4.0 introduces a vector-less transfer of test data, and provides an ATE independent interactive user interface that enables real-time hierarchical diagnostics for logic, memory and phase-lock loops. "This is the first known solution to successfully bridge the disciplines of IC design, IC diagnostics and characterization, and IC manufacturing test to create a seamless flow to system test," said Vinod Agarwal, LogicVision's president and CEO. "We believe LogicVision's Embedded Test 4.0 will help ensure accurate, highly efficient and cost-effective testing of complex SoCs, benefiting the entire semiconductor industry," he said. ET 4.0 enables automated test generation in chip designs. The product's so-called IC Debug feature enables debugging directly on the tester and provides full access and control of all embedded test controllers within the chip under test. It also includes a LogicVision Database (LVDB) that generates manufacturing-ready test databases. LVDB collects all the necessary information to describe generated and contained embedded test IP for the SoC. This capability enables both vector-less hand-off from design to manufacturing and on-the-fly pattern generation at the tester. ET 4.0 is now available for Solaris and HP-UX operating system.
Related News
- Ambarella licenses the World's First Standard SD MMC 4.0 Host Controller IP core from Arasan Chip Systems
- Faraday's client – Skymedi produced the world's first MultiMediaCard™ 4.0 chip using Faraday's 0.18um Structured ASIC Library
- LogicVision announces new generation embedded test solutions -- LV4 enbling rapid delivery of quality SoCs at lower costs
- PCIe 5.0 & PCIe 4.0 PHYs and Controller IP Cores are available for immediate licensing to maximize your Interface speed for complex SoCs
- InnoGrit adopts M31's optimization solutions of PCIe 4.0/3.0 and ONFi 4.1 I/O IP cores for Artificial Intelligence Storage chips
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |