Dolphin Integration releases the evaluation kit for benchmarking at once Libraries and Memories

Meylan, France – October 08, 2010. Dolphin Integration offers the VEDA benchmark to assist SoC Integrators in their steadfast search for minimizing costs and maximizing the performances of each of their design.

With the VEDA benchmark it is now easy to estimate the area after P&R and the power consumption of any logic design – including RAM, ROM, and Standard Cell Library – when embedding Dolphin Integration’s Panoply to perform a benchmark against any other solution.

So, why should Designers change their evaluation habits?

With traditional evaluation method, assessing the comparative performances of various solutions at SoC level is a tricky endeavor:

• It requires Designers to get an access to a complete evaluation kit for each IP and from each possible provider
• It involves to be suspicious about the benchmarking conditions

Nothing could be easier and faster than performing a benchmark of a specific logic design with the VEDA benchmark:

• Designers receive a file already completed with Dolphin’s most appropriate solutions for a given design
• Then, only few minutes are necessary to complete the file with an alternative solution
• Guidelines for benchmark are explicited

Please follow the link below to get access to the key benefits and features of the VEDA benchmark

http://www.design-reuse.com/sip/view.php?id=24768

Prospective users can receive a VEDA benchmark customized for their design by completing the short registration form:

http://www.dolphin.fr/flip/sesame/sesame_registration.php?prod=VEDA_Benchmark

About Dolphin Integration

Dolphin Integration is up to their charter as the most adaptive and lasting creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation as well as independence and partnerships with Foundries. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components. The strategy is to follow product launches with evolutions addressing future needs, emphasizing resilience to noise and drastic reductions of power-consumption at SoC level, thanks to their own EDA solutions enabling Integration Hardware Modeling (IHM) and Application Hardware Modeling (AHM) as well as early Power and Noise assessment, plus engineering assistance for Risk Control. For more information about Dolphin, visit: www.dolphin.fr/sesame

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