Process Detector (For DVFS and monitoring process variation)
Dolphin Integration launch their unique JAXpower structure for optimized power regulators
Meylan, France – October 15, 2010. Dolphin Integration, the enabler of Mixed Signal Systems-on-Chip (SoC) now provide Integrators with solutions for optimizing Power Management Networks (PMN). Indeed, embedding PMIC functions must not maintain a monolithic structure but must be properly disseminated throughout the SoC. Their JAXpower structure enables networking Power Management, whatever the SoC application schematics. Blocks of readymade regulators are selected to match integrators' needs, depending on the loads of separate Silicon IP, and their specific optimization criteria.
As a result, integrators can reach any optimization compromise: high efficiency, low BoM, low noise, low power or high density, while benefiting from a fast delivery of the network kit. Thanks to a wide possibility of configurations, SoC designers only need a single provider for the entire PMN if they wish for reducing their time to market. Dolphin Integration provides either FAEs support or can deliver a Custom Training Package for the diverse modeling needs of a realistic PMN.
Virtual Components of Silicon IP from Dolphin are now supplied with their JAXpower regulator:
- High-resolution audio converters benefit from low-noise and low-consumption regulators, while embedding pop-up noise reduction functions, etc.
- Logic blocks (including RAMs and standard cells) benefit from dual voltage regulators enabling autonomous power islet and low-voltage operation.
For more information on this structured approach and the Power Management Network offering, have a look at shCOD95.SP04-Helium2-2V5 presentation sheet, a CODED with an embedded regulator or inquire from the following contact: jazz@dolphin.fr
About Dolphin Integration
Dolphin Integration is up to their charter as the most adaptive and lasting creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation as well as independence and partnerships with Foundries. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components. The strategy is to follow product launches with evolutions addressing future needs, emphasizing resilience to noise and drastic reductions of power-consumption at SoC level, thanks to their own EDA solutions enabling Integration Hardware Modeling (IHM) and Application Hardware Modeling (AHM) as well as early Power and Noise assessment, plus engineering assistance for Risk Control. For more information about Dolphin, visit: www.dolphin.fr/jazz
|
Dolphin Design Hot IP
Related News
- Dolphin Integration enrich their Reusable Power Kit Library DELTA with Linear Regulators optimized for noise sensitive applications
- Dolphin Integration announce a breakthrough in silicon IP for power management
- INGChips selects Dolphin Integration's Power Management IP Platform for its ultra Low Power Bluetooth Low-Energy SoC in 40 nm eFlash
- PixArt Imaging selects voltage regulators IPs from Dolphin Integration for its ultra-low power MCU Sensor in 40 nm
- Dolphin Integration presents its know-how in EDA for safe Power Regulation Networks implementation at ENIAC's THINGS2DO E.U. project final review
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |