English
Free Software Enables Development of IEEE 1149.1-2011 JTAG and IJTAG Based Infrastructure IP for FPGA and SoCs
DOVER, NH-- November 1, 2010 - Intellitech announced today a free version of its NEBULA software to enable FPGA and SoC designers to develop and validate JTAG/IJTAG based infrastructure IP. The software is targeted for designers who want to validate internal JTAG accessible IP blocks and instruments using the PDL language of upcoming 1149.1-2011 and future IEEE P1687. PDL - Procedure Definition Language is common to both standards and enables developers to describe the operation of the JTAG accessible IP. End customers and integrators can then re-use the PDL provided without re-targeting when the IP is integrated into IC level internal JTAG chains. NEBULA version 6.1 is available for free download after registration at the following link http://www.intellitech.com/ijag. Registrations for the software will close after five hundred registrants.
NEBULA supports early versions of the proposed IEEE 1149.1-2011 internal IJTAG test data register definitions and mnemonics and PDL. Spreadsheet views give the user easy access to read and write internal JTAG registers using data values or mnemonic words thus removing the need to count register bits. The software also includes the TCL/TK scripting language for creating robust user-defined and freely deployable instrument and IP GUIs.
NEBULA communicates to the SoC or FPGA via two freely downloadable software packages, ISIS for VCS and iCableserverX for Xilinx USB JTAG cables. ISIS, Intellitech's Simulation Interface Server runs on 64-bit Linux and communicates with VCS to drive JTAG in simulation. SoC developers can record ATE vectors from PDL and TCL scripts running on NEBULA while it communicates over ISIS to the simulation. The software is limited to three devices in the JTAG chain which is suitable for SoCs, and evaluation boards from Digilent, Xilinx, Altera, Hi-tech Global and others. This limitation can be overcome using Intellitech's JTAG IP or JTAG devices in the target design.
About Intellitech
http://www.intellitech.com/company/about.asp
|
||||||
Related News
- Altera Quartus II Software v14.1 Enables TFLOPS Performance in Industry's First FPGA with Hardened Floating Point DSP Blocks
- Ceva Joins Arm Total Design to Accelerate Development of End-to-End 5G SoCs for Infrastructure and NTN Satellites
- Blue Pearl Software and NanoXplore SAS team to Accelerate Development and Verification of Radiation Hardened FPGA Designs
- Renesas Launches Integrated Development Environment That Enables ECU-Level Automotive Software Development Without Hardware
- Corigine Delivers a Next-Generation Prototyping System for ASIC and Pre-Silicon Software Development
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |